Abstract
Among all the fault tolerance (FT) techniques developed over the years, Dual-core lock-step techniques have emerged as an effective approach to enhance the fault tolerance capabilities of these systems. However, they cannot withstand Hard Errors occurring in the architecture, and they have certain drawbacks for checkpoints and restore methodologies necessary to save and restore the correct state of the core. This paper shows an execution paradigm within a new architectural approach to overcome the disadvantages related to the long checkpointing/restoring procedures that affect the classical lock-step architectures, also improving the hard, destructive faults resilience, leveraging the advantages of the already published dynamic-TMR technique inside the Klessydra-dfT03 architecture.
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Barbirotta, M. et al. (2024). Heterogeneous Tightly-Coupled Dual Core Architecture Against Single Event Effects. In: Bellotti, F., et al. Applications in Electronics Pervading Industry, Environment and Society. ApplePies 2023. Lecture Notes in Electrical Engineering, vol 1110. Springer, Cham. https://doi.org/10.1007/978-3-031-48121-5_2
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DOI: https://doi.org/10.1007/978-3-031-48121-5_2
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