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Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative

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Applications in Electronics Pervading Industry, Environment and Society (ApplePies 2023)

Abstract

This paper presents a cycle-accurate verification environment for the Crypto-Tile, a cryptographic accelerator integrated into the EPI General Purpose Processor. The focus of this work is to provide a robust methodology for validating the functionality and performance of the Crypto-Tile. The verification environment includes an in-depth examination of the internal architecture and operational aspects of the Crypto-Tile, allowing for accurate modelling of hardware components and emulation of Direct Memory Access (DMA) operations. Developers can leverage this environment to simulate and verify their C-Code implementations, utilizing the functions available in the Crypto-Tile library or creating custom libraries. The verification process involves using the 32-bit AXI4 interface for communication between the processor and the Crypto-Tile while emulating DMA operations to ensure accurate testing.

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References

  1. Intel Software Guard Extensions (Intel SGX)—Key Management on the 3rd Generation Intel Xeon Scalable Processor. Technical report, Intel (2019)

    Google Scholar 

  2. Coppolino L, D’Antonio S, Mazzeo G, Romano L (2019) A comprehensive survey of hardware-assisted security: from the edge to the cloud. Internet Things 6:100055

    Article  Google Scholar 

  3. Crocetti L, Baldanzi L, Bertolucci M, Sarti L, Carnevale B, Fanucci L (2019) A simulated approach to evaluate side-channel attack countermeasures for the advanced encryption standard. Integration 68:80–86 September

    Article  Google Scholar 

  4. Di Matteo S, Baldanzi L, Crocetti L, Nannipieri P, Fanucci L, Saponara S (2021) Secure elliptic curve crypto-processor for real-time iot applications. Energies 14(15)

    Google Scholar 

  5. Gupta S (2023) An edge-computing based Industrial Gateway for Industry 4.0 using ARM TrustZone technology. J Ind Inf Integr 33:100441

    Google Scholar 

  6. Kovač M et al (2022) European processor initiative: Europe’s approach to exascale computing

    Google Scholar 

  7. McKeen F, Alexandrovich I, Berenzon A, Rozas CV, Shafi H, Shanbhogue V, Savagaonkar UR (2013) Innovative instructions and software model for isolated execution, vol 10

    Google Scholar 

  8. Nannipieri P, Bertolucci M, Baldanzi L, Crocetti L, Di Matteo S, Falaschi F, Fanucci L, Saponara S (2021) SHA2 and SHA-3 accelerator design in a 7 nm technology within the European processor initiative. Microprocess Microsyst 87

    Google Scholar 

  9. Nannipieri P, Di Matteo S, Baldanzi L, Crocetti L, Belli J, Fanucci L, Saponara S (2021) True random number generator based on fibonacci-galois ring oscillators for FPGA. Appl Sci (Switzerland) 11(8)

    Google Scholar 

  10. Nannipieri P, Matteo S, Baldanz L, Crocetti L, Zulberti L, Saponara S, Fanucci L (2022) VLSI design of advanced-features AES crypto processor in the framework of the european processor initiative. IEEE Trans Very Large Scale Integr (VLSI) Syst 30(2):177–186

    Google Scholar 

  11. Nannipieri P, Crocetti L, Matteo SD, Fanucci L, Saponara S (2023) Hardware design of an advanced-feature cryptographic tile within the european processor initiative. IEEE Trans Comput 1–14

    Google Scholar 

  12. Pinto S, Santos N (2019) Demystifying arm trust zone: a comprehensive survey. ACM Comput Surv (CSUR) 51(6):1–36

    Google Scholar 

  13. Zulberti L, Di Matteo S, Nannipieri P, Saponara S, Fanucci L (2022) A script-based cycle-true verification framework to speed-up hardware and software co-design: performance evaluation on ECC accelerator use-case. Electronics (Switzerland) 11(22)

    Google Scholar 

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Acknowledgements

This work was partially funded by the European Union’s Horizon 2020 research and innovation programme “European Processor Initiative” (grant agreement No. 101036168, EPI SGA2) and partly supported by the Italian Ministry of University and Research (MUR) with the project CN4—CN00000023 of Recovery and Resilience Plan (PNRR) program, grant agreement No. I53C22000720001, and in the framework of the FoReLab project (Departments of Excellence).

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Correspondence to Pietro Nannipieri .

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Nannipieri, P., Di Matteo, S., Crocetti, L., Zulberti, L., Fanucci, L., Saponara, S. (2024). Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative. In: Bellotti, F., et al. Applications in Electronics Pervading Industry, Environment and Society. ApplePies 2023. Lecture Notes in Electrical Engineering, vol 1110. Springer, Cham. https://doi.org/10.1007/978-3-031-48121-5_54

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  • DOI: https://doi.org/10.1007/978-3-031-48121-5_54

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-031-48120-8

  • Online ISBN: 978-3-031-48121-5

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