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Efficiently Testable Circuits Without Conductivity

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Theory of Cryptography (TCC 2023)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 14371))

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Abstract

The notion of “efficiently testable circuits” (ETC) was recently put forward by Baig et al. (ITCS’23). Informally, an ETC compiler takes as input any Boolean circuit C and outputs a circuit/inputs tuple \((C',\mathbb {T})\) where (completeness) \(C'\) is functionally equivalent to C and (security) if \(C'\) is tampered in some restricted way, then this can be detected as \(C'\) will err on at least one input in the small test set \(\mathbb {T}\). The compiler of Baig et al. detects tampering even if the adversary can tamper with all wires in the compiled circuit. Unfortunately, the model requires a strong “conductivity” restriction: the compiled circuit has gates with fan-out up to 3, but wires can only be tampered in one way even if they have fan-out greater than one. In this paper, we solve the main open question from their work and construct an ETC compiler without this conductivity restriction. While Baig et al. use gadgets computing the AND and OR of particular subsets of the wires, our compiler computes inner products with random vectors. We slightly relax their security notion and only require that tampering is detected with high probability over the choice of the randomness. Our compiler increases the size of the circuit by only a small constant factor. For a parameter \(\lambda \) (think \(\lambda \le 5\)), the number of additional input and output wires is \(|C|^{1/\lambda }\), while the number of test queries to detect an error with constant probability is around \(2^{2\lambda }\).

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Notes

  1. 1.

    The conductivity assumption for the PC compiler from [24] is slightly stronger than ours, as they additionally assume that “faults on the output side of a NOT gate propagate to the input side”.

  2. 2.

    Ensuring non-conductivity by making sure the fan-out is 1 is done for clarity of exposition. To get a fan-out 1 circuit our complied circuit requires numerous \(\textsf{COPY}\) gates. In an actual physical circuit any of those \(\textsf{COPY}\) gates can be simply removed by increasing the fan-out of the input wire to that gate by one.

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Authors and Affiliations

  1. ISTA, Zurich, Switzerland

    Mirza Ahad Baig & Krzysztof Pietrzak

  2. Visa Research, Santa Clara, USA

    Suvradip Chakraborty

  3. University of Warsaw, Warsaw, Poland

    Stefan Dziembowski, Małgorzata Gałązka & Tomasz Lizurej

  4. IDEAS NCBR, Warsaw, Poland

    Stefan Dziembowski & Tomasz Lizurej

Authors
  1. Mirza Ahad Baig
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  2. Suvradip Chakraborty
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  3. Stefan Dziembowski
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  4. Małgorzata Gałązka
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  5. Tomasz Lizurej
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  6. Krzysztof Pietrzak
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Correspondence to Mirza Ahad Baig .

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  1. Apple, Cupertino, CA, USA

    Guy Rothblum

  2. NTT Research, Sunnyvale, CA, USA

    Hoeteck Wee

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Baig, M.A., Chakraborty, S., Dziembowski, S., Gałązka, M., Lizurej, T., Pietrzak, K. (2023). Efficiently Testable Circuits Without Conductivity. In: Rothblum, G., Wee, H. (eds) Theory of Cryptography. TCC 2023. Lecture Notes in Computer Science, vol 14371. Springer, Cham. https://doi.org/10.1007/978-3-031-48621-0_5

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