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Deductive Verification of Parameterized Embedded Systems Modeled in SystemC

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Verification, Model Checking, and Abstract Interpretation (VMCAI 2024)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 14500))

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Abstract

Major strengths of deductive verification include modular verification and support for functional properties and unbounded parameters. However, in embedded systems, crucial safety properties often depend on concurrent process interactions, events, and time. Such properties are global in nature and thus difficult to verify in a modular fashion. Furthermore, the execution and scheduling semantics of industrially used embedded system design languages such as SystemC are typically only informally defined. In this paper, we propose a deductive verification approach for embedded systems that are modeled with SystemC. Our main contribution is twofold: 1) We provide a formal encoding and an automated transformation of SystemC designs for verification with the VerCors deductive verifier. 2) We present a novel approach for invariant construction to abstractly capture global dependencies. Our encoding enables an automated formalization and deductive verification of parameterized SystemC designs, and the invariant construction enables local reasoning about global properties with comparatively low manual effort. We demonstrate the applicability of our approach on three parameterized case studies, including an automotive control system.

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Notes

  1. 1.

    While implementations of the simulation semantics often use a deterministic execution order, the IEEE standard does not define any such order [26].

  2. 2.

    Static sensitivity is subsumed by dynamic sensitivity and a hierarchical design can be flattened by using, for example, prefixing.

  3. 3.

    For simplicity, we speak of arrays here. In our implementation, all collections have the PVL-intrinsic type , which reduces verification time.

  4. 4.

    Note also that, despite not necessarily increasing the state space, more processes and events also mean that the representation of each state in the RASI will have more atomic conditions.

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Authors and Affiliations

  1. University of Twente, Enschede, The Netherlands

    Philip Tasche, Raúl E. Monti & Marieke Huisman

  2. University of Münster, Münster, Germany

    Stefanie Eva Drerup, Pauline Blohm & Paula Herber

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  1. Philip Tasche
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Correspondence to Philip Tasche .

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  1. CISPA Helmholtz Center for Information Security, Saarbrücken, Germany

    Rayna Dimitrova

  2. Tel Aviv University, Tel Aviv, Israel

    Ori Lahav

  3. New York University, New York, NY, USA

    Sebastian Wolff

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Tasche, P., Monti, R.E., Drerup, S.E., Blohm, P., Herber, P., Huisman, M. (2024). Deductive Verification of Parameterized Embedded Systems Modeled in SystemC. In: Dimitrova, R., Lahav, O., Wolff, S. (eds) Verification, Model Checking, and Abstract Interpretation. VMCAI 2024. Lecture Notes in Computer Science, vol 14500. Springer, Cham. https://doi.org/10.1007/978-3-031-50521-8_9

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