Abstract
In image processing, a connected components algorithm is a method used to identify and label the different objects or regions present in a digital image. This algorithm can be useful for a variety of image processing tasks, such as object recognition, image segmentation, and feature extraction. This work presents the implementation of a single-pass algorithm on an FPGA-based device suitable for high-performance edge computing vision applications, the Ultra96-V2 computing board. The design and implementation of the IP core have faced challenges using the AMD-Xilinx HLS workflow and tools, which require efficient and optimized use of resources, as well as the re-engineering of the algorithm to comply with the requirements imposed by the development framework. The performance of the proposed accelerator has been thoroughly analysed using the YACCLAB benchmarking framework against a high-end and a low-end CPU. The results show an expected loss in performance due to memory and clock frequency limitations. However, concerning energy efficiency, the hardware multicore architecture outperforms the software alternatives with an improvement between two and five times, depending on the size and complexity of the images.
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Acknowledgment
This research has been funded by the European Union’s H2020 programme under grant agreement no. 857159 (SHAPES project) and by the Spanish Ministry of Economy and Competitiveness (MINECO) under the TALENT project (PID2020-116417RB-C4, subproject 1) and the MIRATAR project (TED2021-132149B-C41).
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Mira, J.L. et al. (2024). High Performance Connected Components Accelerator for Image Processing in the Edge. In: Skliarova, I., Brox Jiménez, P., Véstias, M., Diniz, P.C. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2024. Lecture Notes in Computer Science, vol 14553. Springer, Cham. https://doi.org/10.1007/978-3-031-55673-9_15
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