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A Safety-Critical, RISC-V SoC Integrated and ASIC-Ready Classic McEliece Accelerator

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Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC 2024)

Abstract

Security is an integral part of ensuring the integrity of safety-critical systems. Safety-critical systems with extremely long-lifespan, such as the ones employed in the space and automotive industry, need additional security measures that can guarantee the thwarting of both current and future attacks. In that respect, the future advent of large-scale quantum computers, could potentially compromise the security of such systems leading to catastrophic consequences. To this end, in this paper we present the integration of the post-quantum cryptosystem of Classic McEliece (CM) in an open-source platform for high-performance safety-critical systems (SELENE). The SELENE project proposed a new family of safety-critical computing platforms, which builds upon open source components such as the RISC-V instruction set architecture, GNU/Linux, and the Jailhouse hypervisor. This work capitalizes on the modularity of the SELENE hardware platform and proposes a high-performance and constant-time HLS-based accelerator of the encoding and decoding subroutines of CM. We specifically present the first integration of a CM accelerator in a Linux-capable and RISC-V based System-on-Chip (SoC). Our experiments show significant speedups of up to 4.9\(\mathbf {\times }\) and 198\(\mathbf {\times }\) compared to a scalar software implementation of CM encoding and decoding subroutines respectively, executed on an x86 core. We additionally showcase a successful implementation of our accelerator in an ASIC context using the Global Foundries 22 nm technology node operating at \(\mathbf {>1}\) GHz frequency.

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Notes

  1. 1.

    ASIC results in GF22nm technology node are analyzed in Sect. 4.

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Acknowledgements

This work has been partially supported by the European HiPEAC Network of Excellence, by the Spanish Ministry of Science and Innovation MCIN/AEI 10.13039/501100011033 (contracts ACITHEC PID2021-124928NB-I00, PID2019-107255GB-C21 and “Ramón y Cajal” fellowship No. RYC2020-030685-I), by the Generalitat de Catalunya (contract 2021-SGR-00763), by the Agency for Management of University and Research Grants (AGAUR) of the Government of Catalonia under “Ajuts per a la contractació de personal investigador novell” fellowship No. 2019FI B01274 and the grant 2021SGR 00115, by the European Union within the framework of the ERDF of Catalonia 2014–2020 under the DRAC project [001-P-001723], by the project HERMES funded by INCIBE, and by the European NextGenerationEU/PRTR.

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Kostalabros, V., Ribes-González, J., Farràs, O., Moretó, M., Hernandez, C. (2024). A Safety-Critical, RISC-V SoC Integrated and ASIC-Ready Classic McEliece Accelerator. In: Skliarova, I., Brox Jiménez, P., Véstias, M., Diniz, P.C. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2024. Lecture Notes in Computer Science, vol 14553. Springer, Cham. https://doi.org/10.1007/978-3-031-55673-9_20

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  • DOI: https://doi.org/10.1007/978-3-031-55673-9_20

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