Abstract
SPHINCS+ is a signature scheme included in the first NIST post-quantum standard, that bases its security on the underlying hash primitive. As most of the runtime of SPHINCS+ is caused by the evaluation of several hash- and pseudo-random functions, instantiated via the hash primitive, offloading this computation to dedicated hardware accelerators is a natural step. In this work, we evaluate different architectures for hardware acceleration of such a hash primitive with respect to its use-case and evaluate them in the context of SPHINCS+. We attach hardware accelerators for different hash primitives (SHAKE256 and Ascon-Xof for both, full and round-reduced versions) to CPU interfaces having different transfer speeds. We show, that for most use-cases, data transfer determines the overall performance if accelerators are equipped with FIFOs and that reducing the number of rounds in the permutation does not necessarily lead to significant performance improvements when using hardware acceleration.
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Acknowledgments
The authors acknowledge the financial support by the Federal Ministry of Education and Research of Germany in the programme of “Souverän. Digital. Vernetzt.”. Joint project 6G-life, project identification number: 16KISK002.
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Karl, P., Schupp, J., Sigl, G. (2024). The Impact of Hash Primitives and Communication Overhead for Hardware-Accelerated SPHINCS+. In: Wacquez, R., Homma, N. (eds) Constructive Side-Channel Analysis and Secure Design. COSADE 2024. Lecture Notes in Computer Science, vol 14595. Springer, Cham. https://doi.org/10.1007/978-3-031-57543-3_12
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