Abstract
Coarse-Grained Reconfigurable Array (CGRA) architectures are becoming increasingly popular as low-power accelerators in compute and data intensive application domains such as security, multimedia, signal processing, and machine learning. The efficiency of a CGRA is determined by its architectural features and the compiler’s ability to exploit the spatio-temporal configuration. Numerous design optimizations and mapping techniques have been introduced in this direction. However, the execution model has been overlooked, despite its critical role in ensuring the efficient acceleration of applications. Most of the existing CGRA implementations follow a hosted approach i.e., they execute the modulo scheduled innermost loop, entrusting outer loops to the host processor. This increases synchronization overhead with the host, mitigating the benefits of acceleration provided by the CGRA. In this paper, we propose a compilation flow that supports efficient standalone execution of nested loops. Experiments show that the standalone execution model leads to a maximum of \(12.33\times \) and an average of \(6.75\times \) performance improvement compared to the existing hosted execution model. In the proposed model, energy consumption is reduced up to \(14.49\times \) compared to that of the hosted one. We also compared our results with state-of-the-art standalone execution that uses loop flattening and achieved a maximum of \(4.80\times \) speed up with an average of \(2.80\times \).
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Sunny, C., Das, S., Martin, K.J.M., Coussy, P. (2024). Standalone Nested Loop Acceleration on CGRAs for Signal Processing Applications. In: Dias, T., Busia, P. (eds) Design and Architectures for Signal and Image Processing. DASIP 2024. Lecture Notes in Computer Science, vol 14622. Springer, Cham. https://doi.org/10.1007/978-3-031-62874-0_7
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