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Verifying PLC-Automata Against Counterexample Formulas Using Timed Automata

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Real Time and Such

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 15230))

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Abstract

Timed automata due to Rajeev Alur and David Dill are the primary model for verifying properties of real-time systems with a continuous time domain. UPPAAL developed by Kim G. Larsen and Wang Yi and their collaborators is the main tool for practically performing such verifications. However, timed automata are in general not implementable. An automata model that enables implementation on the platform of Programmable Logic Controllers are PLC-Automata introduced by Henning Dierks. By translating them into timed automata, properties of PLC-Automata can be verified. We show this for properties formulated by counterexample formulas. The presentation is based on our book “Real-Time Systems” with Henning Dierks.

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Notes

  1. 1.

    see: i-cav.org/cav-award

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Acknowledgement

The author thanks Christopher Bischopink for suggesting the example in Sect. 3.

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Authors and Affiliations

  1. Carl von Ossietzky University of Oldenburg, Oldenburg, Germany

    Ernst-Rüdiger Olderog

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  1. Ernst-Rüdiger Olderog
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Correspondence to Ernst-Rüdiger Olderog .

Editor information

Editors and Affiliations

  1. Université Grenoble Alpes, VERIMAG, Grenoble, France

    Susanne Graf

  2. Mälardalen University, Västerås, Sweden

    Paul Pettersson

  3. TU Dortmund University, Dortmund, Germany

    Bernhard Steffen

UPPAAL Timed Automata

UPPAAL Timed Automata

Fig. 7.
figure 7

\(\mathcal {T}(\text {Syn}-1)\) as UPPAAL timed automaton

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Fig. 8.
figure 8

The CEX formula (BdStab-4) represented as UPPAAL timed automaton

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Olderog, ER. (2025). Verifying PLC-Automata Against Counterexample Formulas Using Timed Automata. In: Graf, S., Pettersson, P., Steffen, B. (eds) Real Time and Such. Lecture Notes in Computer Science, vol 15230. Springer, Cham. https://doi.org/10.1007/978-3-031-73751-0_5

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  • DOI: https://doi.org/10.1007/978-3-031-73751-0_5

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