Abstract
Multiway circuit partitioning is a key combinatorial optimization problem that appears many times throughout the Very Large Scale Integration (VLSI) design workflow. However, as VLSI designs continue to grow in size and complexity in accordance with Moore’s law, current circuit-partitioning algorithms, which are mostly based on simple heuristics that become easily trapped in local minima, are increasingly hard-pressed to produce high-quality solutions in reasonable amounts of CPU runtime. To address this challenge, this paper proposes a novel circuit-partitioning algorithm that combines Deep Reinforcement Learning (DRL) with the popular Fiduccia-Mattheyses-Sanchis (FMS) circuit-partitioning heuristic. A DRL agent is trained to dynamically apply a perturbation function during the search in order to enable FMS escape local minima and to accelerate convergence towards higher-quality solutions. Experimental results obtained show significant improvements both in solution quality and CPU runtime.
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References
Alpert, C.J.: The ispd98 circuit benchmark suite. In: Proceedings of the 1998 International Symposium on Physical Design, pp. 80–85. ISPD ’98, Association for Computing Machinery, New York, NY, USA (1998). https://doi.org/10.1145/274535.274546
Budak, A.F., Jiang, Z., Zhu, K., Mirhoseini, A., Goldie, A., Pan, D.Z.: Reinforcement learning for electronic design automation: case studies and perspectives: (invited paper). In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 500–505 (2022). https://doi.org/10.1109/ASP-DAC52403.2022.9712578
Buluç, A., Meyerhenke, H., Safro, I., Sanders, P., Schulz, C.: Recent Advances in Graph Partitioning, pp. 117–158. Springer International Publishing, Cham (2016). https://doi.org/10.1007/978-3-319-49487-6_4
Bustany, I., Kahng, A.B., Koutis, I., Pramanik, B., Wang, Z.: Specpart: a supervised spectral framework for hypergraph partitioning solution improvement. In: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design. ICCAD ’22, Association for Computing Machinery, New York, NY, USA (2022). https://doi.org/10.1145/3508352.3549390
Çatalyürek, U., et al.: More recent advances in (hyper)graph partitioning. ACM Comput. Surv. 55(12) (2023). https://doi.org/10.1145/3571808
Chen, S., Cheng, C.: Tutorial on VLSI partitioning. VLSI Des. 11(3), 175–218 (2000). https://doi.org/10.1155/2000/53913
Fiduccia, C., Mattheyses, R.: A linear-time heuristic for improving network partitions. In: 19th Design Automation Conference, pp. 175–181 (1982). https://doi.org/10.1109/DAC.1982.1585498
Gottesbüren, L., Heuer, T., Maas, N., Sanders, P., Schlag, S.: Scalable high-quality hypergraph partitioning. ACM Trans. Algorithms 20(1) (2024). https://doi.org/10.1145/3626527
Karypis, G., Aggarwal, R., Kumar, V., Shekhar, S.: Multilevel hypergraph partitioning: applications in vlsi domain. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7(1), 69–79 (1999). https://doi.org/10.1109/92.748202
Kernighan, B.W., Lin, S.: An efficient heuristic procedure for partitioning graphs. Bell Syst. Tech. J. 49(2), 291–307 (1970). https://doi.org/10.1002/j.1538-7305.1970.tb01770.x
Kim, J., Hwang, I., Kim, Y.H., Moon, B.R.: Genetic approaches for graph partitioning: a survey. In: Proceedings of the 13th Annual Conference on Genetic and Evolutionary Computation, pp. 473–480. GECCO ’11, Association for Computing Machinery, New York, NY, USA (2011). https://doi.org/10.1145/2001576.2001642
Mirhoseini, A., et al.: A graph placement methodology for fast chip design. Nature 594(7862), 207–212 (2021)
Mnih, V., et al.: Playing atari with deep reinforcement learning. CoRR abs/1312.5602 (2013). http://arxiv.org/abs/1312.5602
Ren, H., et al.: Optimizing VLSI implementation with reinforcement learning - iccad special session paper. In: 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), pp. 1–6 (2021). https://doi.org/10.1109/ICCAD51958.2021.9643589
Sanchis, L.: Multiple-way network partitioning. IEEE Trans. Comput. 38(1), 62–81 (1989). https://doi.org/10.1109/12.8730
Schlag, S., Heuer, T., Gottesbüren, L., Akhremtsev, Y., Schulz, C., Sanders, P.: High-quality hypergraph partitioning. ACM J. Exp. Algorithmics 27 (2023). https://doi.org/10.1145/3529090
Watkins, C.J.C.H., Dayan, P.: Q-learning. Mach. Learn. 8(3), 279–292 (1992). https://doi.org/10.1007/BF00992698
Zhu, K., Liu, M., Chen, H., Zhao, Z., Pan, D.Z.: Exploring logic optimizations with reinforcement learning and graph convolutional network. In: 2020 ACM/IEEE 2nd Workshop on Machine Learning for CAD (MLCAD), pp. 145–150 (2020). https://doi.org/10.1145/3380446.3430622
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Siddiqi, U.F., Chuen Cheng, K., Grewal, G., Areibi, S. (2024). Enhancing K-Way Circuit Partitioning: A Deep Reinforcement Learning Methodology. In: Pereira, A.I., et al. Optimization, Learning Algorithms and Applications. OL2A 2024. Communications in Computer and Information Science, vol 2280. Springer, Cham. https://doi.org/10.1007/978-3-031-77426-3_10
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