Abstract
This work presents HyRPF, a hybrid approach for simulating RRAM-based memory blocks and registers on FPGAs. HyRPF combines the accuracy and speed of physical prototypes with the scalability and cost-effectiveness of computer simulations. Our approach is implemented in the form of advanced IP blocks, which facilitate rapid prototyping of computer architectures that integrate RRAM memory. These blocks are intended to replace existing memory seamlessly, allowing for quick implementation of system designs and tests while also addressing critical challenges such as functional and non-functional device properties. Statistical models are utilized to account for various temporal and non-temporal variabilities and environmental conditions, including temperature influences. Additionally, energy consumption estimates can be conducted. The performance of our approach is validated by simulating register files and caches within a RISC-V processor architecture. The evaluation shows that HyRPF achieves functional accuracy comparable to purely software-based solutions and faithfully reproduces all essential properties of RRAM devices with minimal resource utilization, while outperforming them in terms of simulation speed and achieving a performance faster than real-time. HyRPF has the potential to significantly accelerate the development and testing of RRAM-based systems, providing researchers and engineers with a versatile and easy-to-use tool that balances accuracy and efficiency.
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Reiser, D. et al. (2025). HyRPF: Hybrid RRAM Prototyping on FPGA. In: Carro, L., Regazzoni, F., Pilato, C. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2024. Lecture Notes in Computer Science, vol 15226. Springer, Cham. https://doi.org/10.1007/978-3-031-78377-7_14
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