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Formal Specification Level

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Models, Methods, and Tools for Complex Chip Design

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 265))

Abstract

The steadily increasing complexity of the design of embedded systems led to the development of both an elaborated design flow that includes various abstraction levels and corresponding methods for synthesis and verification. However, until today the initial system specification is provided in natural language which is manually translated into a formal implementation e.g. at the Electronic System Level (ESL) by means of SystemC in a time-consuming and error-prone process.In this chapter, we envision a design flow which incorporates a Formal Specification Level (FSL) aiming at bridging the gap between the informal textbook specification and the formal ESL implementation. Modeling languages such as UML or SysML are envisaged for this purpose. Recent accomplishments towards this envisioned design flow, namely the automatic derivation of formal models from natural language descriptions, verification of formal models in the absence of an implementation, and code generation techniques, are briefly reviewed.

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Notes

  1. 1.

    In the following, we focus on UML in combination with OCL, while the general concepts are similarly applicable to other modeling languages as well.

  2. 2.

    Note that SystemC is just a representative for any high-level object-oriented hardware description language and can readily be replaced.

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Acknowledgements

This work was supported by the German Research Foundation (DFG) within the Reinhart Koselleck project DR 287/23-1. The authors would like to thank Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, and Julia Seiter for interesting and helpful discussions.

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Authors and Affiliations

  1. Group of Computer Architecture, University of Bremen, Bremen, Germany

    Rolf Drechsler, Mathias Soeken & Robert Wille

  2. Cyber-Physical Systems, DFKI GmbH, Bremen, Germany

    Rolf Drechsler, Mathias Soeken & Robert Wille

Authors
  1. Rolf Drechsler
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  2. Mathias Soeken
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  3. Robert Wille
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Corresponding author

Correspondence to Rolf Drechsler .

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Editors and Affiliations

  1. Institute of Computer Technology, Vienna University of Technology, Vienna, Austria

    Jan Haase

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Drechsler, R., Soeken, M., Wille, R. (2014). Formal Specification Level. In: Haase, J. (eds) Models, Methods, and Tools for Complex Chip Design. Lecture Notes in Electrical Engineering, vol 265. Springer, Cham. https://doi.org/10.1007/978-3-319-01418-0_3

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  • DOI: https://doi.org/10.1007/978-3-319-01418-0_3

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-01417-3

  • Online ISBN: 978-3-319-01418-0

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