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Haifa Verification Conference

HVC 2013: Hardware and Software: Verification and Testing pp 214–229Cite as

Formal Specification of an Erase Block Management Layer for Flash Memory

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Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 8244))

Abstract

This work presents a formal specification and an implementation of an erase block management layer and a formal model of the flash driver interface. It is part of our effort to construct a verified file system for flash memory. The implementation supports wear-leveling, handling of bad blocks and asynchronous erasure of blocks. It uses additional data structures in RAM for efficiency and relies on a model of the flash driver, which is similar to the Memory Technology Device (MTD) layer of Linux. We specify the effects of unexpected power failure and subsequent recovery. All models are mechanized in the interactive theorem prover KIV.

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References

  1. Börger, E., Stärk, R.F.: Abstract State Machines—A Method for High-Level System Design and Analysis. Springer (2003)

    Google Scholar 

  2. Butterfield, A., Ó Catháin, A.: Concurrent models of flash memory device behaviour. In: Oliveira, M.V.M., Woodcock, J. (eds.) SBMF 2009. LNCS, vol. 5902, pp. 70–83. Springer, Heidelberg (2009)

    Chapter  Google Scholar 

  3. Butterfield, A., Freitas, L., Woodcock, J.: Mechanising a formal model of flash memory. Sci. Comput. Program. 74(4), 219–237 (2009)

    Article  MathSciNet  MATH  Google Scholar 

  4. Butterfield, A., Woodcock, J.: Formalising flash memory: First steps. In: IEEE Int. Conf. on Engineering of Complex Computer Systems, pp. 251–260 (2007)

    Google Scholar 

  5. Chung, T.-S., Park, D.-J., Park, S., Lee, D.-H., Lee, S.-W., Song, H.-J.: A survey of flash translation layer. J. Syst. Archit. 55(5-6), 332–343 (2009)

    Article  Google Scholar 

  6. Intel Corp. Intel Flash File System Core Reference Guide, version 1. Technical report, Intel Corporation (2004)

    Google Scholar 

  7. Damchoom, K., Butler, M.: Applying Event and Machine Decomposition to a Flash-Based Filestore in Event-B. In: Oliveira, M.V.M., Woodcock, J. (eds.) SBMF 2009. LNCS, vol. 5902, pp. 134–152. Springer, Heidelberg (2009)

    Chapter  Google Scholar 

  8. Samsung Electronics. Page program addressing for MLC NAND application note (2009), http://www.samsung.com

  9. Ernst, G., Schellhorn, G., Haneberg, D., Pfähler, J., Reif, W.: A Formal Model of a Virtual Filesystem Switch. In: Proc. of Software and Systems Modeling (SSV), pp. 33–45 (2012)

    Google Scholar 

  10. Ernst, G., Schellhorn, G., Haneberg, D., Pfähler, J., Reif, W.: Verification of a Virtual Filesystem Switch. In: Proc. of Verified Software, Theories Tools and Experiments (to appear, 2013)

    Google Scholar 

  11. Intel Corporation, et al.: Open NAND Flash Interface Specification (June 2013), http://www.onfi.org

  12. Freitas, L., Woodcock, J., Butterfield, A.: POSIX and the Verification Grand Challenge: A Roadmap. In: ICECCS 2008: Proc. of the 13th IEEE Int. Conf. on Engineering of Complex Computer Systems (2008)

    Google Scholar 

  13. Gal, E., Toledo, S.: Algorithms and Data Structures for flash memory. ACM Computing Surveys, 138–163 (2005)

    Google Scholar 

  14. Gleixner, T., Haverkamp, F., Bityutskiy, A.: UBI - Unsorted Block Images (2006), http://www.linux-mtd.infradead.org/doc/ubidesign/ubidesign.pdf

  15. Hoare, C.A.R.: The verifying compiler: A grand challenge for computing research. Journal of the ACM 50(1), 63–69 (2003)

    Article  Google Scholar 

  16. Hunter, A.: A brief introduction to the design of UBIFS (2008), http://www.linux-mtd.infradead.org/doc/ubifs_whitepaper.pdf

  17. INCITS. ATA/ATAPI Command Set - 2 (ACS-2), Revision 2 (August 3, 2009)

    Google Scholar 

  18. Joshi, R., Holzmann, G.J.: A mini challenge: build a verifiable filesystem. Formal Aspects of Computing 19(2) (June 2007)

    Google Scholar 

  19. Kang, E., Jackson, D.: Formal Modeling and Analysis of a Flash Filesystem in Alloy. In: Börger, E., Butler, M., Bowen, J.P., Boca, P. (eds.) ABZ 2008. LNCS, vol. 5238, pp. 294–308. Springer, Heidelberg (2008)

    Chapter  Google Scholar 

  20. Kang, E., Jackson, D.: Designing and analyzing a flash file system with alloy. Int. J. Software and Informatics 3(2-3), 129–148 (2009)

    Google Scholar 

  21. Knight, F.: TRIM - DRAT/RZAT clarifications for ATA8-ACS2, Revision 2 (February 23, 2010)

    Google Scholar 

  22. Memory Technology Device (MTD) and Unsorted Block Images (UBI) Subsystem of Linux, http://www.linux-mtd.infradead.org/index.html

  23. Odersky, M., Spoon, L., Venners, B.: Programming in Scala: A Comprehensive Step-by-step Guide, 1st edn. Artima Incorporation, USA (2008)

    Google Scholar 

  24. Pfähler, J., Ernst, G., Haneberg, D., Schellhorn, G., Reif, W.: KIV models and proofs of MTD, UBI and abstract UBI (2013), http://www.informatik.uni-augsburg.de/swt/projects/flash.html

  25. Reeves, G., Neilson, T.: The Mars Rover Spirit FLASH anomaly. In: Aerospace Conference, pp. 4186–4199. IEEE Computer Society (2005)

    Google Scholar 

  26. Reif, W., Schellhorn, G., Stenzel, K., Balser, M.: Structured specifications and interactive proofs with KIV. In: Bibel, W., Schmitt, P. (eds.) Automated Deduction—A Basis for Applications, vol. II, pp. 13–39. Kluwer, Dordrecht (1998)

    Chapter  Google Scholar 

  27. Schellhorn, G., Tofan, B., Ernst, G., Reif, W.: Interleaved programs and rely-guarantee reasoning with ITL. In: Proc. of TIME, pp. 99–106. IEEE Computer Society (2011)

    Google Scholar 

  28. Schierl, A., Schellhorn, G., Haneberg, D., Reif, W.: Abstract Specification of the UBIFS File System for Flash Memory. In: Cavalcanti, A., Dams, D.R. (eds.) FM 2009. LNCS, vol. 5850, pp. 190–206. Springer, Heidelberg (2009)

    Chapter  Google Scholar 

  29. The Open Group. The Open Group Base Specifications Issue 7, IEEE Std 1003.1, 2008 edn. (2008), http://www.unix.org/version3/online.html (login required)

  30. UBI - Out-of-Band Data Area, http://www.linux-mtd.infradead.org/faq/ubi.html

  31. UBIFS - Unstable Bits Issue, http://www.linux-mtd.infradead.org/doc/ubifs.html

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Author information

Authors and Affiliations

  1. Institute for Software & Systems Engineering, University of Augsburg, Germany

    Jörg Pfähler, Gidon Ernst, Gerhard Schellhorn, Dominik Haneberg & Wolfgang Reif

Authors
  1. Jörg Pfähler
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  2. Gidon Ernst
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  3. Gerhard Schellhorn
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  4. Dominik Haneberg
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  5. Wolfgang Reif
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Editor information

Editors and Affiliations

  1. Department of Electrical Engineering and Computer Science, CSE #4645 - ACAL Lab, University of Michigan, 2260 Hayward Avenue, 48109-2121, Ann Arbor, MI, USA

    Valeria Bertacco

  2. Inventors for the Digital World, inria, Bat C, Burean C213, Campus Universitaire de Beaulieu, 35042, Rennes Cedex, France

    Axel Legay

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© 2013 Springer International Publishing Switzerland

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Pfähler, J., Ernst, G., Schellhorn, G., Haneberg, D., Reif, W. (2013). Formal Specification of an Erase Block Management Layer for Flash Memory. In: Bertacco, V., Legay, A. (eds) Hardware and Software: Verification and Testing. HVC 2013. Lecture Notes in Computer Science, vol 8244. Springer, Cham. https://doi.org/10.1007/978-3-319-03077-7_15

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  • DOI: https://doi.org/10.1007/978-3-319-03077-7_15

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-03076-0

  • Online ISBN: 978-3-319-03077-7

  • eBook Packages: Computer ScienceComputer Science (R0)

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