Abstract
In order to increase design productivity of SoC (System on Chip) systems, there is a need to move from implementation-driven design at Register Transfer Language (RTL) to higher levels of abstraction. This move introduces a shift in the development of electronic systems, which has been put into practice as Electronic System Level (ESL) design. The importance of ESL has become reality with Transaction Level Modeling (TLM) standard TLM-2.0 [1]. The C++-based system modeling language SystemC perfectly supports TLM and hence is well-accepted for ESL design in industry.
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References
Transaction-Level Modeling (TLM) 2.0 Reference Manual, http://www.systemc.org/downloads/standards/
Herber, P., Pockrandt, M., Glesner, S.: Transforming systemc transaction level models into uppaal timed automata. In: Singh, S., Jobstmann, B., Kishinevsky, M., Brandt, J. (eds.) MEMOCODE, pp. 161–170. IEEE (2011)
Ebnenasir, A., Hajisheykhi, R., Kulkarni, S.S.: Facilitating the design of fault tolerance in transaction level systemc programs. Theor. Comput. Sci. 496, 50–68 (2013)
Hajisheykhi, R., Ebnenasir, A., Kulkarni, S.: Analysis of permanent, transient, and message faults in transaction level systemc programs, Tech. Rep. MSU-CSE-13-6, Department of Computer Science, Michigan State University, East Lansing, Michigan (July 2013)
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Hajisheykhi, R., Ebnenasir, A., Kulkarni, S.S. (2013). Modeling and Analyzing Timing Faults in Transaction Level SystemC Programs. In: Higashino, T., Katayama, Y., Masuzawa, T., Potop-Butucaru, M., Yamashita, M. (eds) Stabilization, Safety, and Security of Distributed Systems. SSS 2013. Lecture Notes in Computer Science, vol 8255. Springer, Cham. https://doi.org/10.1007/978-3-319-03089-0_25
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DOI: https://doi.org/10.1007/978-3-319-03089-0_25
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