Abstract
Transactional memory (TM) has emerged as an alternative to the lock-based parallel programming model offering an effective and optimistic management of concurrency. Recently, TM is being experimented in the context of high performance computing. Many applications in that area spent a large amount of computing time in irregular reduction operations, so their efficient parallelization is of utmost importance. This paper explores how to address irregular reductions in the TM model, analyzing which support needs to be added to the TM system to deal with reductions as a special case of conflicting memory accesses.
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Gonzalez-Mesa, M.A., Quislant, R., Gutierrez, E., Plata, O. (2013). Exploring Irregular Reduction Support in Transactional Memory. In: Kołodziej, J., Di Martino, B., Talia, D., Xiong, K. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2013. Lecture Notes in Computer Science, vol 8285. Springer, Cham. https://doi.org/10.1007/978-3-319-03859-9_22
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DOI: https://doi.org/10.1007/978-3-319-03859-9_22
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