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Software Transactional Memory Friendly Slot Schedulers

  • Conference paper
Distributed Computing and Internet Technology (ICDCIT 2014)

Part of the book series: Lecture Notes in Computer Science ((LNISA,volume 8337))

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Abstract

In this paper, we discuss the design space of highly concurrent linearizable data structures for slot scheduling. We observe that it is not possible to have high fairness across threads, and maximize throughput of the entire system simultaneously. Lock free algorithms are very fast, yet very unfair, and wait free algorithms follow the reverse trend. We thus propose a class of algorithms using software transactional memory (STM) that are in the middle of the spectrum. They equitably balance fairness and throughput, and are much simpler to design and verify.

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References

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  5. Extended Discussion on STM Friendly Slot Scheduling Algorithms, posted at   http://www.cse.iitd.ac.in/~srsarangi/files/papers/stmlong.pdf

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Author information

Authors and Affiliations

  1. Computer Science Department, IIT Delhi, New Delhi, India

    Pooja Aggarwal & Smruti R. Sarangi

Authors
  1. Pooja Aggarwal
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  2. Smruti R. Sarangi
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Editor information

Editors and Affiliations

  1. School of Technology & Computer Science, Tata Institute of Fundamental Research, Homi Bhabha Road, Colaba, 400005, Mumbai, India

    Raja Natarajan

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© 2014 Springer International Publishing Switzerland

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Aggarwal, P., Sarangi, S.R. (2014). Software Transactional Memory Friendly Slot Schedulers. In: Natarajan, R. (eds) Distributed Computing and Internet Technology. ICDCIT 2014. Lecture Notes in Computer Science, vol 8337. Springer, Cham. https://doi.org/10.1007/978-3-319-04483-5_8

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  • DOI: https://doi.org/10.1007/978-3-319-04483-5_8

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-04482-8

  • Online ISBN: 978-3-319-04483-5

  • eBook Packages: Computer ScienceComputer Science (R0)

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