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A Framework for Verification of SystemC Designs Using SystemC Waiting State Automata

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Integration of Reusable Systems

Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 263))

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Abstract

The SystemC waiting-state automaton is a compositional abstract formal model for verifying properties of SystemC at the transaction level within a delta-cycle: the smallest simulation unit time in SystemC. In this chapter, how to extract automata for SystemC components where we distinguish between threads and methods in SystemC. Then, we propose an approach based on a combination of symbolic execution and computing fixed points via predicate abstraction to infer relations between predicates generated during symbolic execution. Finally, we define how to apply model checking to prove the correctness of the abstract analysis.

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Notes

  1. 1.

    a Galois connection is a pair of functions \((\alpha ,\gamma )\) satisfying \(\alpha (\gamma (\widetilde{s}))= \widetilde{s}\) and \(\varphi \Rightarrow \gamma (\alpha (\varphi )\)). Given \(\gamma \), \(\alpha \) is implicitly defined by \(\alpha (\varphi )=\cap \{\widetilde{s}\in \widetilde{S}| \varphi \Rightarrow \gamma (\widetilde{s})\}.\)

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Authors and Affiliations

  1. ENSTA ParisTech, Department of Electronics and Computer Engineering, 91762, Palaiseau, France

    Nesrine Harrath & Bruno Monsuez

  2. CNAM Paris, VESPA/CEDRIC, 75003, Paris, France

    Nesrine Harrath & Kamel Barkaoui

Authors
  1. Nesrine Harrath
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  2. Bruno Monsuez
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  3. Kamel Barkaoui
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Corresponding author

Correspondence to Nesrine Harrath .

Editor information

Editors and Affiliations

  1. Laboratoire de Communication dans les Systèmes Informatiques, Ecole Nationale Supérieure d’Informatique, Algiers, Algeria

    Thouraya Bouabana-Tebibel

  2. SPAWAR Systems Center Pacific, San Diego, USA

    Stuart H. Rubin

Appendix A: A Symbolic execution for the example program

Appendix A: A Symbolic execution for the example program

  • inst. \(1-2\)

    $$\underbrace{(max=0)\wedge (i=0)}_{\varphi _0}\rightarrow $$
    figure c

  • inst.3

    $$(max=0)\wedge (i=0)\wedge (i<T.length)\rightarrow $$
    figure d
    $$\wedge (max=0)\wedge (i=0)\wedge (i\ge T.length)\rightarrow $$
    figure e

  • inst.4 \( (max'=0)\wedge (i=0)\wedge (i<T.length)\wedge (T[i]>max')\wedge (max=T[i])\rightarrow \)

    figure f

    \(\wedge (max=0)\wedge (i=0)\wedge (i<T.length)\wedge (T[i]\le max)\rightarrow \)

    figure g
    $$\wedge (max=0)\wedge (i=0)\wedge (i\ge T.length)\rightarrow $$
    figure h

    \(\Longleftrightarrow \) \( {\left\{ \begin{array}{ll} (max'=0)\wedge (i=0)\wedge (i<T.length)\wedge \\ (T[i]>max')\wedge (max=T[i])\\ \bigvee \\ (max=0)\wedge (i=0)\wedge (i<T.length)\wedge \\ (T[i]\le max) \end{array}\right. } \) \(\rightarrow \)

    figure i

  • inst.5

    $$ \underbrace{\begin{array}{l}(max'=0)\wedge (i'=0)\wedge (i'<T.length)\wedge (T[i']>max')\wedge (max=T[i'])\\ \bigvee (max=0)\wedge (i'=0)\wedge (i'<T.length)\wedge (T[i']\le max)\wedge (i=i'+1)\end{array}}_{\varphi _1} \rightarrow $$
    figure j

  • \( \varphi _0 \vee \varphi _1 \rightarrow \)

    figure k

  • \( 0\le i \wedge i\le T.length \wedge \forall j.(0\le j < i\rightarrow T[j]\le max)\rightarrow \)

    figure l

  • \( 0\le i \wedge \forall j.(0\le j < i\rightarrow T[j]\le max)\wedge i\ge T.length \rightarrow \)

    figure m

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Harrath, N., Monsuez, B., Barkaoui, K. (2014). A Framework for Verification of SystemC Designs Using SystemC Waiting State Automata. In: Bouabana-Tebibel, T., Rubin, S. (eds) Integration of Reusable Systems. Advances in Intelligent Systems and Computing, vol 263. Springer, Cham. https://doi.org/10.1007/978-3-319-04717-1_4

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  • DOI: https://doi.org/10.1007/978-3-319-04717-1_4

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  • Online ISBN: 978-3-319-04717-1

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