Abstract
Side Channel Analysis (SCA), which has gained wide attentions during the past decade, has arisen as one of the most critical metrics for the cryptographic algorithm security evaluation. Typical SCA analyzes the data-dependent variations inspected from side channel leakages, such as power and electromagnetism (EM), to disclose intra secrets from cryptographic implementations on varying platforms, like microprocessor, FPGA, etc. Dual-rail Precharge Logic (DPL) has proven to be an effective logic-level countermeasure against classic correlation analysis by means of dual-rail compensation protocol. However, the DPL design is hard to be automated on FPGA, and the only published approach is subject to a simplified and partial AES core. In this paper, we present a novel implementation approach applied to a complete AES-128 crypto algorithm. This proposal bases on a partition mechanism which splits the whole algorithm to submodules and transform individuals to DPL format respectively. The main flavor lies within its highly symmetric dual-rail routing networks inside each block, which significantly reduces the routing bias between each routing pair in DPL. This paper describes the overall repair strategy and technical details. The experimental result shows a greatly elevated success rate during the routing repair phase, from lower than 60% to over 84% for Xilinx Virtex-5 FPGA in SASEBO-GII evaluation board.
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Tu, C., He, W., Gao, N., de la Torre, E., Liu, Z., Liu, L. (2014). A Progressive Dual-Rail Routing Repair Approach for FPGA Implementation of Crypto Algorithm. In: Huang, X., Zhou, J. (eds) Information Security Practice and Experience. ISPEC 2014. Lecture Notes in Computer Science, vol 8434. Springer, Cham. https://doi.org/10.1007/978-3-319-06320-1_17
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DOI: https://doi.org/10.1007/978-3-319-06320-1_17
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