A High-Throughput Unrolled ZUC Core for 100Gbps Data Transmission

Abstract

In this paper, we propose a high-throughput encryption and decryption IP core based on ZUC, in order to satisfy the demand of confidentiality and data integrity in modern multi-gigabit communication system. Till now, a popular method for improvement of hardware implementation on ZUC is to apply pipeline technology to promote the design’s performance. At the same time, there is another method to take advantage of the unrolling technology into hardware implementation. However, we find that the existing unrolled architecture on ZUC cannot improve the performance efficiently, even may reduce the performance. In this paper, we present our novel optimization techniques: computation rescheduling and single-feedback initialization for improving throughput. Combining these techniques, we propose two unrolled architectures: x2-ZUC and x3-ZUC, both of which significantly improve the performance both on FPGA and ASIC. The performance of our new unrolled architecture on FPGA in Virtex-5 is at least 63.5% higher than the previous design. Meanwhile, on ASIC of 65 nm technology the best performance of our architecture is up to 100 Gbps, which achieves the highest throughput for the hardware implementation of ZUC. The evaluation result suggests that our novel unrolled architecture with the high throughput is suitable for the high-speed and high-throughput data transmissions at a bandwidth of 100 Gbps.

The work is supported by a grant from the National High Technology Research and Development Program of China (863 Program, No.2013AA01A214) and the National Basic Research Program of China (973 Program, No. 2013CB338001).