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A Survey on Design and Implementation of Floating Point Adder in FPGA

  • Conference paper
Progress in Systems Engineering

Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 366))

Abstract

FPGAs are widely being used in high performance and scientific computing applications. FPGAs are suitable for such applications when conventional processors implementations do not satisfy the realtime and high performance requirements. Most of these applications demand high numerical stability and accuracy, and wide range of numbers. Hence, they are usually based on floating point. Implementing floating point unit in FPGA is one of the crucial issues of hardware implementations. Floating point addition is the most frequent floating point operation and takes most of the scientific operation. It is a costly operation in terms of time and hardware. The main objectives of implementing floating point in FPGA are to achieve high performance with less area, increase the throughput, and decrease the latency. This review paper presents a survey on floating point addition algorithms and techniques, and the implementation of floating point adder in FPGA.

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References

  1. L. Daoud, D. Zydek, and H. Selvaraj: A Survey of High Level Synthesis Languages, Tools, and Compilers for Reconfigurable High Performance Computing. In: Advances in Systems Science. Springer (2014) 483–492, DOI: 10.1007/978-3-319-01857-7_47.

  2. G.Chmaj, K. Walkowiak, M. Tarnawski, and M. Kucharzak: Heuristic Algorithms for Optimization of Task Allocation and Result Distribution in Peer-to-Peer Computing Systems. International Journal of Applied Mathematics and Computer Science 22(3) (2012) 733–748, DOI: 10.2478/v10006-012-0055-0.

    Google Scholar 

  3. G. Chmaj, H. Selvaraj, and L. Gewali: Tracker-Node Model for Energy Consumption in Reconfigurable Processing Systems. In: Advances in Systems Science. Springer (2014) 503–512, DOI: 10.1007/978-3-319-01857-7_49.

  4. L. Daoud, and V. Goulart: High Performance Bitwise OR Based Submesh Allocation for 2D Mesh-Connected CMPs. In: Proceedings of the Euromicro Conference on Digital System Design (DSD), IEEE (2013) 73–77, DOI: 10.1109/DSD.2013.134.

    Google Scholar 

  5. L. Daoud, M. E. Ragab,and V. Goulart: Faster Processor Allocation Algorithms for Mesh-Connected CMPs. In: Proceedings of the Euromicro Conference on Digital System Design (DSD), IEEE (2011) 805–808, DOI: 10.1109/DSD.2011.107.

  6. D. Zydek, G. Chmaj, and S. Chiu: Modeling Computational Limitations in H-Phy and Overlay-NoC Architectures. The Journal of Supercomputing (2013) 1–20, DOI: 10.1007/s11227-013-0932-9.

    Google Scholar 

  7. D. Zydek: Processor Allocator for Chip Multiprocessors. PhD thesis, University of Nevada, Las Vegas, USA (2010)

    Google Scholar 

  8. IEEE Computer Society: IEEE Standard for Floating-Point Arithmetic. (Aug. 29, 2008)

    Google Scholar 

  9. S. F. Oberman, H. Al-Twaijry, and M. J. Flynn: The SNAP Project: Design of Floating Point Arithmetic Units. In: Proceedings of the 13th IEEE Symposium on Computer Arithmetic, IEEE (1997) 156–165

    Google Scholar 

  10. J. Liang, R. Tessier, and O. Mencer: Floating Point Unit Generation and Evaluation for FPGAs. In: Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE (2003) 185–194

    Google Scholar 

  11. Vojin G. Oklobdzija: An Algorithmic and Novel Design of a Leading Zero Detector Circuit: Comparison with Logic Synthesis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2(1) (1994) 124–128

    Article  Google Scholar 

  12. E. Hokenek, and K. Montoye: Leading-Zero Anticipator (LZA) in the IBM RISC System/6000 Floating-Point Execution Unit. IBM Journal of Research and Development 34 (1990)

    Google Scholar 

  13. N. Quach, and M. J. Flynn: Leading One Prediction–Implementation, Generalization, and Application. Computer Systems Laboratory, Stanford University (1991)

    Google Scholar 

  14. H. Suzuki, H. Morinaka, H. Makino, Y. Nakase, K. Mashiko, and T. Sumi: Leading-zero Anticipatory Logic for High-Speed Floating Point Addition. IEEE Journal of Solid-State Circuits 31 (1996)

    Google Scholar 

  15. P. M. Farmwald: On the Design of High Performance Digital Arithmetic Units. Technical report, Lawrence Livermore National Lab, CA (USA) (1981)

    Google Scholar 

  16. A. Beaumont-Smith, N. Burgess, S. Lefrere, and C-C. Lim: Reduced Latency IEEE Floating-Point Standard Adder Architectures. In: Proceedings of the 14th IEEE Symposium on Computer Arithmetic, IEEE (1999) 35–42

    Google Scholar 

  17. P-M. Seidel, and G. Even: On the Design of Fast IEEE Floating-Point Adders. In: Proceedings of the 15th IEEE Symposium on Computer Arithmetic, IEEE (2001) 184–194

    Google Scholar 

  18. M. M. Ozbilen, and M. Gok: A Multi-Precision Floating-Point Adder. In: Porceedings of Research in Microelectronics and Electronics, IEEE (2008) 117–120

    Google Scholar 

  19. R. N. Giri, and M. K. Pandit: Pipelined Floating-Point Arithmetic Unit (FPU) for Advanced Computing Systems using FPGA. International Journal of Engineering and Advanced Technology (IJEAT) (2012) 2249–8958

    Google Scholar 

  20. S. Xing, and W. Yu: FPGA Adders: Performance Evaluation and Optimal Design. Design & Test of Computers, IEEE 15(1) (1998) 24–29

    Article  Google Scholar 

  21. Milos Ercegovac, and Tomas Lang: Digital Arithmetic. Access Online via Elsevier (2003)

    Google Scholar 

  22. P. S. Gollamudi, M. Kamaraju: Design of High Performance IEEE- 754 Single Precision (32 bit) Floating Point Adder Using VHDL. International Journal of Engineering Research & Technology 2 (2013)

    Google Scholar 

  23. I. O. Flores, M. Jimenez, and D. Rodriguez: Optimizing the Implementation of Floating Point Units for FPGA Synthesis. In: Proceedings of Computing Research Conference CRC2002. (2002)

    Google Scholar 

  24. A. Malik, D. Chen, DY. Choi, M. H. Lee, and S-B. ko: Design Tradeoff Analysis of Floating-Point Adders in FPGAs. Canadian Journal of Electrical and Computer Engineering 33(3/4) (2008) 169–175

    Google Scholar 

  25. E. Roesler, and B. Nelson: Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture. In: Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. Springer (2002) 637–646

    Google Scholar 

  26. J. D. Bruguera, and T. Lang: Leading-One Prediction with Concurrent Position Correction. IEEE Transactions on Computers 48(10) (1999) 1083–1097

    Article  Google Scholar 

  27. A. M. Nielsen, D. W. Matula, C. N. Lyu, and G. Even: An IEEE Compliant Floating-Point Adder that Conforms with the Pipelined Packet-Forwarding Paradigm. IEEE Transactions on Computers 49(1) (2000) 33–47 007.

    Google Scholar 

  28. W-C. Park, S-W. Lee, O-Y. Kwon,T-D. HAN and S-D. Kim: Floating Point Adder/Subtractor Performing IEEE Rounding and Addition/Subtraction in Parallel. IEICE transactions on Information and Systems 79(4) (1996) 297–305

    Google Scholar 

  29. N. Quach, N. Takagi, and M. Flynn: On Fast IEEE Rounding. Computer Systems Laboratory, Stanford University (1991)

    Google Scholar 

  30. W. B. Ligon III, S. McMillan, G. Monn, K. Schoonover, F. Stivers, and K. D. Underwood: A Re-evaluation of the Practicality of Floating-Point Operations on FPGAs. In: Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, IEEE (1998) 206–215

    Google Scholar 

  31. G. Govindu, L. Zhuo, S. Choi, and V. Prasanna: Analysis of High-Performance Floating-Point Arithmetic on FPGAs. In: Proceedings of the 18th International Symposium on Parallel and Distributed Processing, IEEE (2004) 149–156

    Google Scholar 

  32. A. Malik, and S-B. Ko: Effective Implementation of Floating-Point Adder Using Pipelined LOP in FPGAs. In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, IEEE (2005) 706–709

    Google Scholar 

  33. P. Karlstrom, A. Ehliar, and D. Liu: High performance, Low Latency FPGA Based Floating Point Adder and Multiplier Units in a Virtex 4. In: Proceedings of the 24th Norchip Conference, IEEE (2006) 31–34

    Google Scholar 

  34. A. Amaricai, M. Vladutiu, L. Prodan, M. Udrescu, and O. Boncalo: Exploiting Parallelism in Double Path Adders’ Structure for Increased Throughput of Floating Point Addition. In: Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, IEEE (2007) 132–137

    Google Scholar 

  35. S. Ghosh, P. Bhattacharyya, and A. Dutta: FPGA Based Implementation of a Double Precision IEEE Floating-Point Adder. In: Proceedings of the 7th International Conference on Intelligent Systems and Control (ISCO), IEEE (2013) 271–275

    Google Scholar 

  36. Y. Huijing, Y. Fan, and H. Dandan: High Performance FPGA Implementation of Floating Point Addition. Applied Mechanics and Materials 380 (2013) 3316–3319

    Google Scholar 

  37. H. Anand, D. Vaithiyanathan, R. Seshasayanan: Optimized Architecture for Floating Point Computation Unit. In: Proceedings of the 2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT), IEEE (2013) 1–5

    Google Scholar 

  38. J. D. Bruguera, and T. Lang: Rounding in Floating-Point Addition Using a Compound Adder. University of Santiago de Compostela, Spain Internal Report (2000)

    Google Scholar 

  39. S. F. Oberman: Design Issues in High Performance Floating Point Arithmetic Units. PhD thesis, Stanford University (1996)

    Google Scholar 

  40. N. T. Quach, and M. J. Flynn: An Improved Algorithm for High-Speed Floating-Point Addition. Computer Systems Laboratory, Stanford University (1990)

    Google Scholar 

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Author information

Authors and Affiliations

  1. Department of Electrical Engineering, Idaho State University, Pocatello, ID, USA

    Luka Daoud & Dawid Zydek

  2. Department of Electrical and Computer Engineering, University of Nevada, Las Vegas, NV, USA

    Henry Selvaraj

Authors
  1. Luka Daoud
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  2. Dawid Zydek
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  3. Henry Selvaraj
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Corresponding author

Correspondence to Luka Daoud .

Editor information

Editors and Affiliations

  1. University of Nevada at Las Vegas, Las Vegas, Nevada, USA

    Henry Selvaraj

  2. Department of Electrical Engineering, Idaho State University, Pocatello, Idaho, USA

    Dawid Zydek

  3. University of Nevada at Las Vegas, Las Vegas, Nevada, USA

    Grzegorz Chmaj

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Daoud, L., Zydek, D., Selvaraj, H. (2015). A Survey on Design and Implementation of Floating Point Adder in FPGA. In: Selvaraj, H., Zydek, D., Chmaj, G. (eds) Progress in Systems Engineering. Advances in Intelligent Systems and Computing, vol 366. Springer, Cham. https://doi.org/10.1007/978-3-319-08422-0_129

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  • DOI: https://doi.org/10.1007/978-3-319-08422-0_129

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-08421-3

  • Online ISBN: 978-3-319-08422-0

  • eBook Packages: EngineeringEngineering (R0)

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