Abstract
Multi-core architecture is the necessity of today's world. Now Moore's law has gone, speed of processors can not be increase because, we have reached in the limit of physics law. Further increase of speed of single processor is not possible. Energy requirement is the biggest hurdle of the multi-core architecture. Their are some problems, because of which performance of multi-core architecture is not increasing. In this research work we have focused on identification of parameters which are responsible for the performance improvement. Our aim is to balance the value of these parameters and analysis of the effect on performance. With the help of the simulation we will increase the speed of multi-core architecture.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
http://software.intel.com/en-us/blogs/2008/12/31/top-10-challenges-in-parallel-computing
Advanced Computer Architecture, parallelism, scalability, programmability, Kai hwang 2nd ed. McGraw-Hill, 01-Feb-2003
Bryan Schauer “Multi core Processors – A Necessity” Pro Quest Discovery Guides, September 2008
Raghavan Raman, “Compiler Support for Work-Stealing Parallel Runtime Systems”, Ph.D. dissertation, Dept. Computer Science, Rice University, Houston, Texas, May 2009
Damian A. Mallon, et al., “Performance Evaluation of MPI, UPC and OpenMP on Multi-core Architectures” in under Project TIN2007-67537-C03-02, Spain.
Dmitri Perelman, “Exploiting Parallelism of Multi-Core Architectures”, Ph.D dissertation, Department of Electrical Engineering, Israel Institute of technology, Haifa Israel September 2012.
Kakoullie, E. et al., “Intelligent Hot-spot Prediction for Network-on-Chip-Based Multi-core Systems” in computer aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.61 no.3, pp. 418 – 431, 2012.
Tudor, B.M. And Young Meng Teo, “Understanding Off-Chip Memory Contention of Parallel Programs in Multi-core Systems”, IEEE Conference in Parallel Processing (ICCP), Taipei, Singapore, 2011, pp. 602 - 611
Shahrivari, S & Sharifi, M, “Task-Oriented Programming: A Suitable Programming Model for Multi-core and Distributed Systems”, IEEE Conference in Parallel and Distributed Computing (ISPDC), Cluj Napoca, Iran, 2011, pp. 139 - 144.
Bini, E et al., Resource Management on Multi-core Systems: The ACTORS Approach, published in IEEE Conference in Micro, 2011, pp. 72-81.
Khan, et al. “Improving Multi-Core Performance Using Mixed-Cell Cache Architecture”, in High Performance Computer Architecture (HPCA2013), IEEE 19th International Symposium, Shenzhen, China, 2013, pp. 119 - 130
Ubal, R et al. “Multi2Sim: A Simulation Framework to Evaluate Multi-core-Multithreaded Processors”, in Computer Architecture and High Performance Computing,19th International Symposium, Rio Grande do Sul, 2007 pp. 62-68
Durate, F and Wong, S “Cache-Based Memory Copy Hardware Accelerator for Multi-core Systems”, Published in Computers, IEEE Transactions, (Volume:59, issue:11), 2010, pp. 1494-1507.
Magnus Broberg, “Performance prediction and improvement techniques for parallel programs in multi processors”, Ph.D dissertation, Department of software Eng. & computer SC., Blekinge institute of technology Sweden, 2002
Julian Bui et al.,“Understanding Performance Issues on both Single Core and Multi-core Architecture”, ACM conference in Computer Organizatione’07, Charlottesvill, 2007
N. Ramasubramanian et al. “Performance of cache memory subsystems for multi-core architectures”, in International Journal of Computer Science Engineering and Applications, (IJCSEA) on vol.1, no.5, October 2011
Mohanty et al. “Performance Evaluation of Multi-core Processors with Varied Interconnect Networks”, in Advanced Computing Networking and Security (ADCONS), 2nd International Conference, Mangalore, India, 2013, pp. 7-11
Acknowledgements
The authors thanks to management of Chameli Devi Group of Institutions, Indore, M.P. India for providing excellent research enviourment in the college. A Special thanks to the Chairman Shri Vinod Kumar Agrawal ji, CDGI Indore, India for motivating to the faculties of the institutioon on research activities.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2015 Springer International Publishing Switzerland
About this paper
Cite this paper
Shukla, S.K., Murthy, C., Chande, P.K. (2015). Parameter Trade-off And Performance Analysis of Multi-core Architecture. In: Selvaraj, H., Zydek, D., Chmaj, G. (eds) Progress in Systems Engineering. Advances in Intelligent Systems and Computing, vol 366. Springer, Cham. https://doi.org/10.1007/978-3-319-08422-0_59
Download citation
DOI: https://doi.org/10.1007/978-3-319-08422-0_59
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-08421-3
Online ISBN: 978-3-319-08422-0
eBook Packages: EngineeringEngineering (R0)