Abstract
SysML is a modeling language that can be used for the modeling of embedded systems. It is rich enough to model critical and complex embedded systems. The available modeling tools have made the modeling of such large and complex systems much easier. They provide sufficient support for the specification of functional requirements in the elicitation phase as well as in the design phase by graphical modeling. These systems must be properly validated and verified before their manufacturing and deployment in order to increase their reliability and reduce their maintenance cost. In this paper, we have proposed a methodology for the modeling and verification of embedded systems in parallel and distributed environments. We demonstrate the suitability of the framework by applying it on the case study of embedded security system. The parallel model checking tool DiVinE has been used because the available sequential verification tools either fail or show poor performance. DiVinE supports Linear Temporal Logic (LTL) for defining nonfunctional requirements and DVE language for specifying models. First,the case study is modeled using SysML’s state machine diagrams and then semantics are described to translate these state machine diagrams to DVE based model. The translated model is verified against specified LTL properties using DiVinE.
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References
O.M.G. OMG System Modeling Language (OMG SysML) specification. Specification document of System Modeling Language (SysML) (June 2012)
Vanderperren, Y., Dehaene, W.: SysML_SE_applied_to_SoC.pdf, http://www.omgsysml.org/SysML_SE_applied_to_SoC.pdf
SysML Tools, http://www.sysmltools.com/ (accessed September 24, 2013)
Bouyer, P.: Model-checking Timed Temporal Logics. In: Bouyer, P. (ed.) Proceedings of the 5th Workshop on Methods for Modalities (M4M5 2007). Electronic Notes in Theoretical Computer Science, vol. 231, pp. 323–341 (March 25, 2009)
Barnat, J., et al.: DiVinE 3.0 – An Explicit-State Model Checker for Multithreaded C & C++ Programs. In: Sharygina, N., Veith, H. (eds.) CAV 2013. LNCS, vol. 8044, pp. 863–868. Springer, Heidelberg (2013)
Siegel, S.F.: Verifying Parallel Programs with MPI-Spin 2007, http://pvmmpi07.lri.fr/tutorial2.html (accessed November 2, 2013)
Basit Ur Rahim, M.A., Arif, F., Ahmad, J.: Parallel verification of UML using DiVinE tool. In: 2013 5th International Conference on Computer Science and Information Technology (CSIT), Amman, Jordan, March 27-28 (2013)
Mashiyat, A.S., Rabbi, F., Wang, H., MacCaull, W.: An automated translator for model checking time constrained workflow systems. In: Kowalewski, S., Roveri, M. (eds.) FMICS 2010. LNCS, vol. 6371, pp. 99–114. Springer, Heidelberg (2010)
Jarraya, Y., Alawneh, L., Hassaine, F., Bebbabi, M.: A unified approach for verification and validation of systems and software. In: 13th Annual IEEE International Symposium and Workshop on Engineering of Computer Based Systems, ECBS 2006, Potsdam, March 27-30 (2006)
Debbabi, M., Jarraya, Y., Soeanu, A., Mourad, D.: Automatic verification and performance analysis of tme-constrained sysML activity diagrams. In: 14th Annual IEEE International Conference and Workshops on the Engineering of Computer-based Systems, ECBS 2007, Tucson, AZ, March 26-29 (2007)
Viehl, A., Sander, B., Bringmann, O., Rosenstie, W.: Integrated requirement evaluation of non-functional. In: Forum on Specification, Verification and Design Languages, FDL 2008, Stuttgart, September 23-25 (2008)
Marcello, M., Murillo, L.G., Prevostini, M.: Model-based design space exploration for RTES with SysML and MARTE. In: Forum on Specification, Verification and Design Languages, FDL 2008, Stuttgart, September 23-25 (2008)
Kawahara, R., Nakamura, H.: Verification of embedded system’s specification using collaborative simulation of SysML and simulink models. In: International Conference on Model-based Systems Engineering, MBSE 2009, Haifa, March 2-5 (2009)
Petin, J.F., Evrot, D., Morel, G., Lamy, P.: Combining SysML and formal models for safety requirements verification. In: 22nd International Conference on Software & Systems Engineering and their Applications, Paris, November 1-5
Linhares, M., de Oliveira, R., Farines, J., Vernadat, F.: Introducing the modeling and verification process in SysML. In: ETFA 2007 - 12th IEEE Int. Conf. on Emerging Technologies and Factory Automation, Patras, September 25-28 (2007)
Mazzini, S., Puri, S., Mari, F., Melatti, I., Enrico, T.: Formal verification at system level. In: DAta Systems in Aerospace (DASIA), Org. EuroSpace, Canadian Space Agency, CNES, ESA, EUMETSAT, Instanbul, Turkey (2009)
Knorreck, D., Apvrille, L.: TEPE: A SysML language for time-sonstrained property modeling and formal verification. ACM SIGSOFT Software Engineering Notes 1 (January 2011)
Basit Ur Rahim, M.A., Arif, F., Ahmad, J.: Formal verification of sequence diagram using DiVinE. In: International Conference on Computer Software and Applications (ICCSA 2014), Hammamet, Tunisia (January 2014)
Basit Ur Rahim, M.A., Arif, F., Ahmad, J.: Modeling of real-time embedded system using SysML and its verification using UPPAAL and DiVinE. In: International Conference on Software Engineering and Service Science (ICSESS 2014), Beijing, Chine, June 2-29 (2014)
Petin, J.F., Evrot, D., Morel, G., Lamy, P.: Combining SysML and formal models for safety requirements verification. In: 22nd International Conference on Software & Systems Engineering and their Applications (ICSSEA 2010), Paris, France, December 7-9 (2010)
Jarraya, Y., Debbabi, M.: Formal Specification and Probabilistic Verification of SysML Activity Diagrams. In: Sixth International Symposium on Theoretical Aspects of Software Engineering, TASE 2012, Beijing, China, July 4-6 (2012)
COMPASS, COMPASS_WP_03.pdf, http://www.compass-research.eu/ (accessed April 14, 2014)
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Basit Ur Rahim, M.A., Arif, F., Ahmad, J. (2014). Modeling of Embedded System Using SysML and Its Parallel Verification Using DiVinE Tool. In: Murgante, B., et al. Computational Science and Its Applications – ICCSA 2014. ICCSA 2014. Lecture Notes in Computer Science, vol 8583. Springer, Cham. https://doi.org/10.1007/978-3-319-09156-3_38
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DOI: https://doi.org/10.1007/978-3-319-09156-3_38
Publisher Name: Springer, Cham
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