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Temporal Logic and Fair Discrete Systems

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Handbook of Model Checking

Abstract

Temporal logic has been used by philosophers to reason about the way the world changes over time. Its modern use in specification and verification of systems describes the evolution of states of a program/design giving rise to descriptions of executions. Temporal logics can be classified by their view of the evolution of time as either linear or branching. In the linear-time view, we see time ranging over a linear total order and executions are sequences of states. When the system has multiple possible executions (due to nondeterminism or reading input) we view them as separate possible evolutions and the system has a set of possible behaviors. In the branching-time view, a point in time may have multiple possible successors and accordingly executions are tree-like structures. According to this view, a system has exactly one execution, which takes the form of a tree. We start this chapter by introducing Fair Discrete Structures, the model on which we evaluate the truth and falsity of temporal logic formulas. Fair Discrete Structures describe the states of a system and their possible evolution. We then proceed with the linear-time view and introduce Propositional Linear Temporal Logic (LTL). We explain the distinction between safety and liveness properties and introduce a hierarchy of liveness properties of increasing expressiveness. We study the expressive power of full LTL and cover extensions that increase its expressive power. We introduce algorithms for checking the satisfiability of LTL and model checking LTL. We turn to the branching-time framework and introduce Computation Tree Logic (CTL). As before, we discuss its expressive power, consider extensions, and cover satisfiability and model checking. We then dedicate some time to examples of formulas in both LTL and CTL and stress the differences between the two. We end with a formal comparison of LTL and CTL and, in view of this comparison, introduce CTL*, a hybrid of LTL and CTL that combines the linear and branching views into one logic.

Comment by Nir Piterman: Sadly, during the preparation of this manuscript, in November 2009, Amir passed away. While I tried to keep the chapter in the spirit of our plans I cannot be sure that Amir would have agreed with the final outcome. All faults and inaccuracies are definitely my own. In addition, opinions or judgements passed in this chapter may not reflect Amir’s view. I would like to take this opportunity to convey my deep gratitude to Amir; my teacher, supervisor, mentor, and friend.

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Author information

Authors and Affiliations

  1. University of Leicester, Leicester, UK

    Nir Piterman

  2. New York University, New York, USA

    Amir Pnueli

  3. The Weizmann Institute of Science, Rehovot, Israel

    Amir Pnueli

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  1. Nir Piterman
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  2. Amir Pnueli
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Correspondence to Nir Piterman .

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Editors and Affiliations

  1. FORE Systems University Professor of Computer Science, Carnegie Mellon University, Pittsburgh, Pennsylvania, USA

    Edmund M. Clarke

  2. Institute of Science and Technology Austria (IST), Klosterneuburg, Austria

    Thomas A. Henzinger

  3. Arbeitsbereich Formal Methods in Systems Engineering, Technische Universität Wien, Wien, Austria

    Helmut Veith

  4. Institut f. Angewandte Informationsverarbeitung und Kommunikationstechnologie (IAIK), Technische Universität Graz, Graz, Austria

    Roderick Bloem

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Piterman, N., Pnueli, A. (2018). Temporal Logic and Fair Discrete Systems. In: Clarke, E., Henzinger, T., Veith, H., Bloem, R. (eds) Handbook of Model Checking. Springer, Cham. https://doi.org/10.1007/978-3-319-10575-8_2

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  • DOI: https://doi.org/10.1007/978-3-319-10575-8_2

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