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Dual CLEFIA/AES Cipher Core on FPGA

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Applied Reconfigurable Computing (ARC 2015)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 9040))

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Abstract

In this paper a compact high throughput dual-cipher hardware structure is proposed, supporting the novel CLEFIA algorithm and the encryption standard AES. Currently, the more efficient and dedicated structures only allow to process the CLEFIA or the AES encryption algorithms. On the other hand, the existing multi-algorithm processors impose significantly higher area costs and are not able to achieve the throughputs of dedicated solutions. The presented work shows that by adequately scheduling and merging the processing structures, and with the proper use of the existing components in current FPGA technologies, it is possible to achieve a compact and efficient structure capable of computing the novel CLEFIA cipher while also supporting the well implanted AES cipher. Overall, the proposed structure allows for a throughput up to 1Gbps in feedback modes with low area cost, achieving identical efficiency metrics as the existing single cipher state of the art.

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References

  1. Bulens, P., Standaert, F.-X., Quisquater, J.-J., Pellegrin, P., Rouvroy, G.: Implementation of the AES-128 on virtex-5 FPGAs. In: Vaudenay, S. (ed.) AFRICACRYPT 2008. LNCS, vol. 5023, pp. 16–26. Springer, Heidelberg (2008)

    Chapter  Google Scholar 

  2. Chaves, R., Kuzmanov, G., Vassiliadis, S., Sousa, L.: Reconfigurable memory based AES co-processor. In: 20th International on Parallel and Distributed Processing Symposium, IPDPS 2006, p. 8. IEEE (2006)

    Google Scholar 

  3. Chodowiec, P., Gaj, K.: Very compact FPGA implementation of the AES algorithm. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 319–333. Springer, Heidelberg (2003)

    Chapter  Google Scholar 

  4. Drimer, S., Güneysu, T., Paar, C.: DSPs, BRAMs, and a pinch of logic: Extended recipes for AES on FPGAs. ACM Transactions on Reconfigurable Technology and Systems (TRETS) 3(1), 3 (2010)

    Google Scholar 

  5. El Maraghy, M., Hesham, S., Abd El Ghany, M.A.: Real-time efficient FPGA implementation of aes algorithm. In: 2013 IEEE 26th International on SOC Conference (SOCC), pp. 203–208. IEEE (2013)

    Google Scholar 

  6. Elbirt, A.J., Paar, C.: An instruction-level distributed processor for symmetric-key cryptography. IEEE Transactions on Parallel and Distributed Systems 16(5), 468–480 (2005)

    Article  Google Scholar 

  7. Good, T., Benaissa, M.: AES on FPGA from the fastest to the smallest. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 427–440. Springer, Heidelberg (2005)

    Chapter  Google Scholar 

  8. HELION. http://www.heliontech.com

  9. Kashyap, H., Chaves, R.: Secure partial dynamic reconfiguration with unsecured external memory. In: 2014 24th International Conference on Field Programmable Logic and Applications (FPL), pp. 1–7. IEEE (2014)

    Google Scholar 

  10. Kryjak, T., Gorgon, M.: Pipeline implementation of the 128-bit block cipher CLEFIA in FPGA. In: International Conference on Field Programmable Logic and Applications, FPL 2009, pp. 373–378. IEEE (2009)

    Google Scholar 

  11. Liu, Q., Xu, Z., Yuan, Y.: A 66.1 Gbps single-pipeline AES on FPGA. In: 2013 International Conference on Field-Programmable Technology (FPT), pp. 378–381. IEEE (2013)

    Google Scholar 

  12. NIST: FIPS 197: Advanced encryption standard (AES). Federal Information Processing Standards Publication 197, 441–0311 (2001)

    Google Scholar 

  13. Proenca, P., Chaves, R.: Compact CLEFIA implementation on FPGAs. In: 2011 International Conference on Field Programmable Logic and Applications (FPL), pp. 512–517. IEEE (2011)

    Google Scholar 

  14. Rouvroy, G., Standaert, F.X., Quisquater, J.J., Legat, J.: Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications. In: Proceedings of the International Conference on Information Technology: Coding and Computing, ITCC 2004, vol. 2, pp. 583–587. IEEE (2004)

    Google Scholar 

  15. Shirai, T., Shibutani, K., Akishita, T., Moriai, S., Iwata, T.: The 128-Bit blockcipher CLEFIA (Extended Abstract). In: Biryukov, A. (ed.) FSE 2007. LNCS, vol. 4593, pp. 181–195. Springer, Heidelberg (2007)

    Chapter  Google Scholar 

  16. Singh, H., Lee, M.H., Lu, G., Kurdahi, F.J., Bagherzadeh, N., Chaves Filho, E.M.: MorphoSys: An integrated reconfigurable system for data-parallel and computation-intensive applications. IEEE Transactions on Computers 49(5), 465–481 (2000)

    Google Scholar 

  17. Sklavos, N., Koufopavlou, O.: Architectures and VLSI implementations of the AES-proposal Rijndael. IEEE Transactions on Computers 51(12), 1454–1459 (2002)

    Article  MathSciNet  Google Scholar 

  18. Tsunoo, Y., Tsujihara, E., Shigeri, M., Suzaki, T., Kawabata, T.: Cryptanalysis of CLEFIA using multiple impossible differentials. In: International Symposium on Information Theory and its Applications, ISITA 2008, pp. 1–6. IEEE (2008)

    Google Scholar 

  19. Wu, L., Weaver, C., Austin, T.: CryptoManiac: A fast flexible architecture for secure communication. In: Proceedings of the 28th Annual International Symposium on Computer Architecture, pp. 110–119. IEEE (2001)

    Google Scholar 

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Author information

Authors and Affiliations

  1. Instituto Superior Técnico, Universidade de Lisboa / INESC-ID, Rua Alves Redol 9, Lisbon, 1000-029, Portugal

    João Carlos Resende & Ricardo Chaves

Authors
  1. João Carlos Resende
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  2. Ricardo Chaves
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Corresponding author

Correspondence to Ricardo Chaves .

Editor information

Editors and Affiliations

  1. Tohoku University, Sendai, Japan

    Kentaro Sano

  2. National Technical University of Athens, Athens, Greece

    Dimitrios Soudris

  3. Ruhr-Universität Bochum, Bochum, Germany

    Michael Hübner

  4. University of Southern California, Marina del Rey, California, USA

    Pedro C. Diniz

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Resende, J.C., Chaves, R. (2015). Dual CLEFIA/AES Cipher Core on FPGA. In: Sano, K., Soudris, D., Hübner, M., Diniz, P. (eds) Applied Reconfigurable Computing. ARC 2015. Lecture Notes in Computer Science(), vol 9040. Springer, Cham. https://doi.org/10.1007/978-3-319-16214-0_19

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  • DOI: https://doi.org/10.1007/978-3-319-16214-0_19

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-16213-3

  • Online ISBN: 978-3-319-16214-0

  • eBook Packages: Computer ScienceComputer Science (R0)

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