Abstract
This paper addresses an optimal mapping approach which also exploits the partial reconfiguration property of modern CGRAs. Hence this approach is not only suitable for applications which can be accommodated on the available grains but also for larger applications (or a set of applications) that need more grains than what is provided by the CGRA platform. This is achieved by mapping partitions of the application dynamically (during the life time of the application) onto the platform. The proposed mapping flow integrates scheduling, binding and place & route steps into one mapping step using a (Mixed) Integer Linear Problem formulation. The algorithm is implemented using TOMLAB/CPLEX toolbox and we assess its efficacy on a set of 40 synthetic task graphs as well as some real life multimedia applications.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Kolin, P., Chinmaya, D., Mansureh, S.M.: reMORPH - a runtime reconfigurable architecture. In: 15th Euromicro Conference on Digital System Design, September 5–8, Cesme, Izmir, Turkey (2012)
Dick, R.P., Rhodes, D.L., Wolf, W.: TGFF: Task graphs for free. In: Proc. Int. Workshop Hardware/Software Codesign, pp. 97–101 (1998)
Sahu, P.K., Chattopadhyay, S.: A survey on application mapping strategies for Network-on-Chip design (2013)
Bender, A.: MILP based task mapping for heterogeneous multiprocessor systems. In: Proceedings of the Conference on European Design Automation, pp. 190–197. IEEE Computer Society Press, Geneva (1996)
Soumya, J., Sharma, A., Chattopadhyay, S.: Multi-Application Network-on-Chip Design Using Global Mapping and Local Reconfiguration. J. Reconfigurable Techol. Syst. 7, 1–24 (2014)
Carvalho, E., Calazans, N., Moraes, F.: Heuristics for dynamic task mapping in NoC-based heterogeneous MPSoCs. In: 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP 2007) (2007)
Singh, A.K., Srikanthan, T., Kumar, A., Jigang, W.: Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms. J. Sys. Arch. 56, 242–255 (2010)
Singh, A.K., Kumar, A., Srikanthan, T., Ha, Y.: Mapping real-life applications on run-time reconfigurable NoC-based MPSoC on FPGA. In: 2010 International Conference on Field-Programmable Technology (FPT), pp. 365–368 (2010)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2015 Springer International Publishing Switzerland
About this paper
Cite this paper
Moghaddam, M.S., Balakrishnan, M., Paul, K. (2015). Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform. In: Sano, K., Soudris, D., Hübner, M., Diniz, P. (eds) Applied Reconfigurable Computing. ARC 2015. Lecture Notes in Computer Science(), vol 9040. Springer, Cham. https://doi.org/10.1007/978-3-319-16214-0_33
Download citation
DOI: https://doi.org/10.1007/978-3-319-16214-0_33
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-16213-3
Online ISBN: 978-3-319-16214-0
eBook Packages: Computer ScienceComputer Science (R0)