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A Challenge of Portable and High-Speed FPGA Accelerator

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Applied Reconfigurable Computing (ARC 2015)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 9040))

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Abstract

FPGA accelerators can achieve higher computation performance and better power efficiency than CPUs and GPUs, because designers can implement circuits that realize application-specific pipeline dhardware and data supply system. In this paper, we propose a portable and high-speed FPGA accelerator employing USB3.0 which is a datatransfer interface with high versatility and high speed. We choose sorting as a practical application for the FPGA accelerator, and then design and implement the FPGA accelerator that executes sorting at high speed. To demonstrate the high portability, we evaluate the FPGA accelerator with several desktop PCs and laptop PCs. The evaluation result shows the sorting speed of the proposed FPGA accelerator is 1.26x and 2.60x higher than Intel Core i7-3770K operating at 3.5GHz and Intel Core i3-4010U operating at 1.83GHz, respectively. From this evaluation, we also show that the proposed FPGA accelerator has high portability.

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References

  1. Maxeler Technologies. https://www.maxeler.com/

  2. Memory Interface Generator (MIG). http://www.xilinx.com/products/intellectual-property/MIG.htm

  3. Tokushudenshikairo Inc. http://www.tokudenkairo.co.jp/art7/index.html

  4. Kobayashi, R., Kise, K.: Scalable stencil-computation accelerator by employing multiple small fpgas. IPSJ Transactions on Advanced Computing Systems 6(4), 1–13 (2013). http://ci.nii.ac.jp/naid/110009616689/

  5. Koch, D., Torresen, J.: Fpgasort: A high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting. In: Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2011, pp. 45–54. ACM, New York (2011). http://doi.acm.org/10.1145/1950413.1950427

  6. Martinez, J., Cumplido, R., Feregrino, C.: An fpga-based parallel sorting architecture for the burrows wheeler transform. In: International Conference on Reconfigurable Computing and FPGAs, ReConFig 2005, p. 7 (September 2005)

    Google Scholar 

  7. Mueller, R., Teubner, J., Alonso, G.: Sorting networks on fpgas. The VLDB Journal 21(1), 1–23 (2012). http://dx.doi.org/10.1007/s00778-011-0232-z

  8. Putnam, A., Caulfield, A., Chung, E., Chiou, D., Constantinides, K., Demme, J., Esmaeilzadeh, H., Fowers, J., Gopal, G., Gray, J., Haselman, M., Hauck, S., Heil, S., Hormati, A., Kim, J.Y., Lanka, S., Larus, J., Peterson, E., Pope, S., Smith, A., Thong, J., Xiao, P., Burger, D.: A reconfigurable fabric for accelerating large-scale datacenter services. In: 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA), pp. 13–24 (June 2014)

    Google Scholar 

  9. Ratnayake, K., Amer, A.: An fpga architecture of stable-sorting on a large data volume: application to video signals. In: 41st Annual Conference on Information Sciences and Systems, CISS 2007, pp. 431–436 (March 2007)

    Google Scholar 

  10. Sano, K., Hatsuda, Y., Yamamoto, S.: Multi-fpga accelerator forscalablestencil computation with constant memory bandwidth. IEEE Transactions on Parallel and Distributed Systems 25(3), 695–705 (2014)

    Article  Google Scholar 

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Correspondence to Takuma Usui .

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Usui, T., Kobayashi, R., Kise, K. (2015). A Challenge of Portable and High-Speed FPGA Accelerator. In: Sano, K., Soudris, D., Hübner, M., Diniz, P. (eds) Applied Reconfigurable Computing. ARC 2015. Lecture Notes in Computer Science(), vol 9040. Springer, Cham. https://doi.org/10.1007/978-3-319-16214-0_34

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  • DOI: https://doi.org/10.1007/978-3-319-16214-0_34

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-16213-3

  • Online ISBN: 978-3-319-16214-0

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