Abstract
In this paper, we present an improved Mesh of Clusters (MoC) architecture with new hierarchical Switch Box (SB) topology and depopulated intra-cluster interconnect with flexible Rent’s parameter. The aim of this paper is to explore the effect of different architecture parameters like architecture Rent’s, design Rent’s and channel width. Then, we analyze how these factors interact and the way to tune them to satisfy various specific application constraints and quality metrics like power consumption and area. The proposed exploration methodology unifies two procedures which are analytical method based on Rent’s rule modeling and experimental method based on benchmarks circuits implementation. A comparison with VPR mesh architecture shows gains in terms power and area equal respectively to 30% and 32%.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Ahmed, E., et al.: The effect of LUT and cluster size on deep-submicron FPGA performance and density. Very Large Scale Integration (VLSI) Systems (2004)
Landman, B., et al.: On Pin Versus Block Relationship for Partition of Logic Circuits. IEEE Transactions on Computers 20, 1469–1479 (1971)
Betz, V., et al.: Architecture and CAD for Deep-Submicron FPGAs. In: ACL Symposium on Parallel Algorithms and Architectures Series (2000)
Feng, W., et al.: Designing efficient input interconnect blocks for LUT clusters using counting and entropy. In: Proc. of FPGA 2007, Monterey, Calif, USA, p. 2332 (2007)
Marrakchi, Z., et al.: FPGA Interconnect Topologies Exploration. Int. J. Reconfig, Comp. (2009)
Marquart, A., et al.: Using cluster-based logic block and timing-driven packing to improve FPGA speed and density, FPGA, Monterey, p. 3746 (1999)
McMurchie, L., et al.: Pathfinder: A Negotiation-Based Performance-Driven Router for FPGAs. In: Proc. FPGA 1995 (1995)
Lamoureux, J., et al.: Activity Estimation for FieldProgrammable Gate Arrays. In: FPL (2006)
Goeders, J., et al.: VersaPower: Power Estimation for Diverse FPGA Architectures. In: International Conference on Field-Programmable Technology (FPT) (2012)
Rose, J., et al.: The VTR Project: Architecture and CAD for FPGAs from Verilog to Routing. In: FPGA, pp. 77–86 (2012)
DeHon, A., et al.: Compact. Multilayer Layout for Butterfly Fat-Tree. IEEE Trans. VLSI 12(10), 1051–1065 (2004)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2015 Springer International Publishing Switzerland
About this paper
Cite this paper
Chtourou, S., Marrakchi, Z., Pangracious, V., Amouri, E., Mehrez, H., Abid, M. (2015). Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization. In: Sano, K., Soudris, D., Hübner, M., Diniz, P. (eds) Applied Reconfigurable Computing. ARC 2015. Lecture Notes in Computer Science(), vol 9040. Springer, Cham. https://doi.org/10.1007/978-3-319-16214-0_37
Download citation
DOI: https://doi.org/10.1007/978-3-319-16214-0_37
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-16213-3
Online ISBN: 978-3-319-16214-0
eBook Packages: Computer ScienceComputer Science (R0)