Abstract
The paper presents the design of a 60 GHz transceiver, with all active and passive devices integrated on-chip including the antenna, for multi Gbit short-range wireless communications. To minimize circuit complexity and cost an on-off-keying (OOK) modulation scheme is selected as well as a 65 nm bulk CMOS technology instead of more costly CMOS SOI or SiGe or III-V technologies. At transmitter side a differential 2 stage common source power amplifier allows for an output power of about 11 dBm. The receiver includes a cascode LNA with a gain of 11 dB and a noise figure of 4.6 dB, followed by a simple envelop detector. For the on-chip antenna, half-wavelength dipole and inverted-F topologies have been designed. For the transceiver prototype the half-wavelength dipole is selected since it has better gain performance (radiation efficiency of 38 %, a peak directivity of 1.76 and a gain of roughly −2 dBi) although for an higher area occupation. The fully integrated transceiver allows for a data rate of roughly 4 Gbit/s at distances of few meters, being compliant with physical-layer specifications of WirelessHD and WiGig alliances. Work supported by NEWCOM # EU grant.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Gunnarson, S., et al.: 60 GHz single-chip front-end MMICs and systems for multi-Gb/s wireless communication. IEEE JSSC 42(5), 1143–1157 (2007)
Vaughan, J.S.N.: Gigabit Wi-Fi is on its way. IEEE Comput. 43(11), 11–14 (2010)
Zhang, X., et al.: Physical layer design and performance analysis on multi-Gbps millimeter-wave WLAN system. IEEE ICCS10 92–96
Singh, H., et al.: A 60 GHz wireless network for enabling uncompressed video communication. IEEE Comm. Mag. 46(12), 71–78 (2008)
FCC: Code of federal regulation, title 47 telecommunication, Chapter 1, part 15.524 (2004)
Siligaris, A., et al.: CMOS SOI technology for WPAN. Application to 60 GHz LNA. Emerg. Technol. Circuits LNEE 2010 2021(5), 123–130
Niknejad, A.: 0–60 GHz in four years: 60 GHz RF in digital CMOS. IEEE Solid-State Circ. News. 12(2), 5–9 (2007)
Dickson, T.O., et al.: The invariance of characteristic current densities in nanoscale MOSFETs and its impact on algorithmic design methodologies and design porting of Si(Ge) (Bi)CMOS high-speed building blocks. IEEE JSSC 41(8), 1830–1845 (2006)
Voinigescu, S., et al.: Algorithmic design of CMOS LNAs and PAs for 60 GHz radio. IEEE JSSC 42(5), 1044–1057 (2007)
Fonte, A., Saponara, S., et al.: Design of a low noise amplifier with integrated antenna for 60 GHz wireless communications. IEEE IMWS 160–163 (2011)
Juntunen, E., et al.: A 60-GHz 38-pJ/bit 3.5-Gb/s 90-nm CMOS OOK digital radio. IEEE Trans. MTT 58(2), 348–355 (2010)
Chen, Y., et al.: A low-power low-cost fully-integrated 60-GHz transceiver system with OOK modulation and on-board antenna assembly. IEEE JSSC 45(2) (2010)
Saponara, S., et al.: Architectural exploration and design of time-interleaved SAR arrays for low-power and High Speed A/D Converters. IEICE Trans. Electr. E92-C, 843–851 (2009)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer International Publishing Switzerland
About this chapter
Cite this chapter
Saponara, S., Neri, B. (2016). Fully Integrated 60 GHz Transceiver for Wireless HD/WiGig Short-Range Multi-Gbit Connections. In: De Gloria, A. (eds) Applications in Electronics Pervading Industry, Environment and Society. Lecture Notes in Electrical Engineering, vol 351. Springer, Cham. https://doi.org/10.1007/978-3-319-20227-3_17
Download citation
DOI: https://doi.org/10.1007/978-3-319-20227-3_17
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-20226-6
Online ISBN: 978-3-319-20227-3
eBook Packages: EngineeringEngineering (R0)