Abstract
Hardware Description Languages (HDLs) allow for the efficient synthesis of large and complex circuits. Consequently, researchers also investigated their potential in the domain of reversible logic. Here, existing HDL-based synthesis approaches suffer from the significant drawback of employing additional circuit lines in order to buffer intermediate results. In this work, we investigate the possibility of reducing this overhead. For this purpose, an alternative synthesis scheme is proposed and evaluated which aims at a more efficient realization of expressions. The general idea is to re-compute (i.e to undo) sub-expressions as soon as the respective intermediate results are not needed anymore. The observations and discussions result in initial guidelines on how to realize expressions more efficiently as well as a better understanding of the potential of HDL-based synthesis.
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Al-Wardi, Z., Wille, R., Drechsler, R. (2015). Towards Line-Aware Realizations of Expressions for HDL-Based Synthesis of Reversible Circuits. In: Krivine, J., Stefani, JB. (eds) Reversible Computation. RC 2015. Lecture Notes in Computer Science(), vol 9138. Springer, Cham. https://doi.org/10.1007/978-3-319-20860-2_15
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DOI: https://doi.org/10.1007/978-3-319-20860-2_15
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