Abstract
This paper presents a reconfigurable hardware architecture of Forward Error Correction (FEC) coding algorithm for mobile networks, with high throughput on Field Programmable Gate Array (FPGA). The design can be reconfigured for different message length and different generator number, the encoder and decoder has been described using VHDL (VHSIC Hardware Description Language). The decoder has the ability to detect and correct different types and different numbers of errors based on the message length and the length of redundant data. The design has been simulated and tested using ModelSim PE student edition 10.4. Spartan 3 FPGA starter kit from Xilinx has been used for implementing and testing the design in a hardware level.
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El-Medany, W.M. (2015). Reconfigurable Packet FEC Architecture for Mobile Networks. In: Younas, M., Awan, I., Mecella, M. (eds) Mobile Web and Intelligent Information Systems. MobiWIS 2015. Lecture Notes in Computer Science(), vol 9228. Springer, Cham. https://doi.org/10.1007/978-3-319-23144-0_11
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DOI: https://doi.org/10.1007/978-3-319-23144-0_11
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