Abstract
This paper considers some issues to implement the scaler SoC. Because the size and power of SoC are constrained, the bit number to represent the coefficients of scaler kernel and LPF should be limited. In addition, the interpolation position should be located at the quantized phases. We analyze the effects of the various constraints in the performance of scaling system. The simulation results provide the guidance to implement the scaler SoC.
This work was supported in part by the Technology Innovation Program, Industrial Strategic Technology Development Program (Development of Super Resolution Image Scaler for 4Â K UHD), under Grant K10041900, and in part by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (NRF-2015R1A2A2A01006193).
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Lee, SJ., Han, JK. (2015). Performance Analysis of Scaler SoC for 4K Video Signal. In: Ho, YS., Sang, J., Ro, Y., Kim, J., Wu, F. (eds) Advances in Multimedia Information Processing -- PCM 2015. PCM 2015. Lecture Notes in Computer Science(), vol 9315. Springer, Cham. https://doi.org/10.1007/978-3-319-24078-7_28
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DOI: https://doi.org/10.1007/978-3-319-24078-7_28
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