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Spin-Based CMOS-Compatible Devices

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Large-Scale Scientific Computing (LSSC 2015)

Part of the book series: Lecture Notes in Computer Science ((LNISA,volume 9374))

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Abstract

With CMOS feature size rapidly approaching scaling limits the electron spin attracts attention as an alternative degree of freedom for low-power non-volatile devices. Silicon is perfectly suited for spin-driven applications, because it is mostly composed of nuclei without spin and is characterized by weak spin-orbit interaction. Elliot-Yafet spin relaxation due to phonons’ mediated scattering is the main mechanism in bulk silicon at room temperature. Uniaxial stress dramatically reduces the spin relaxation, particularly in thin silicon films. Lifting the valley degeneracy completely in a controllable way by means of standard stress techniques represents a major breakthrough for spin-based devices. Despite impressive progress regarding spin injection, the larger than predicted signal amplitude is still heavily debated. In addition, the absence of a viable concept of spin manipulation in the channel by electrical means makes a practical realization of a device working similar to a MOSFET difficult. An experimental demonstration of such a spin field-effect transistor (SpinFET) is pending for 25 years now, which at present is a strong motivation for researchers to look into the subject. Commercially available CMOS compatible spin-transfer torque magnetic random access memory (MRAM) built on magnetic tunnel junctions possesses all properties characteristic to universal memory: fast operation, high density, and non-volatility. The critical current for magnetization switching and the thermal stability are the main issues to be addressed. A substantial reduction of the critical current density and a considerable increase of the thermal stability are achieved in structures with a recording layer between two vertically sandwiched layers, where the recording layer is composed of two parts in the same plane next to each other. MRAM can be used to build logic-in-memory architectures with non-volatile storage elements on top of CMOS logic circuits. Non-volatility and reduced interconnect losses guarantee low-power consumption. A novel concept for non-volatile logic-in-memory circuits utilizing the same MRAM cells to store and process information simultaneously is proposed.

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Acknowledgements

This work is supported by the European Research Council through the grant #247056 MOSILSPIN.

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Authors and Affiliations

  1. Institute for Microelectronics, TU Wien, Vienna, Austria

    Viktor Sverdlov & Siegfried Selberherr

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  1. Viktor Sverdlov
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  2. Siegfried Selberherr
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Correspondence to Viktor Sverdlov .

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Editors and Affiliations

  1. Bulgarian Academy of Sciences, Sofia, Bulgaria

    Ivan Lirkov

  2. Inst. of Inform. & Communication, Bulgarian Academy of Sciences, Sofia, Bulgaria

    Svetozar D. Margenov

  3. Informatics and Mathematical Modell, Technical University of Denmark, Kongens Lyngby, Denmark

    Jerzy Waśniewski

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Sverdlov, V., Selberherr, S. (2015). Spin-Based CMOS-Compatible Devices. In: Lirkov, I., Margenov, S., Waśniewski, J. (eds) Large-Scale Scientific Computing. LSSC 2015. Lecture Notes in Computer Science(), vol 9374. Springer, Cham. https://doi.org/10.1007/978-3-319-26520-9_4

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  • DOI: https://doi.org/10.1007/978-3-319-26520-9_4

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  • Online ISBN: 978-3-319-26520-9

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