Abstract
The CPU hard cores in programmable System-on-Chips (SoC) often communicate with the soft IP cores in reconfigurable fabric through some dedicated ports. The various data paths corresponding to different ports have different performance characterizations which make them suitable for various applications. This article studies the analytical performance model for transferring data stored in CPU side to FPGA side and vice versa through all different communication ports and data paths available in a typical programmable SoC. The proposed methodology for extracting the cycle accurate delay models is applicable to other similar programmable SoCs. Evaluation experiments identified that the error rate of proposed models are within an acceptable rate of 5 %.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Sadri, M., Weis, C., When, N.: Energy and performance exploration of accelerator coherency port using xilinx ZYNQ. In: 10th FPGAWorld Conference, Copenhagen, Denmark, September 2013
Silva, J., Sklyarov, V., Skliarova, I.: Comparison of on chip communications in Zynq-7000 all programmable systems-on chip. IEEE Embed. Syst. Lett. 7, 1 (2015)
Vogel, P., Marongiu, A., Benini, L.: An evaluation of memory sharing performance for heterogeneous embedded SoCs with many-core accelerators. In: Proceedings of the 2015 International Workshop on Code Optimisation for Multi and Many Cores (2015)
Ding, H., Huang, M.: Improve memory access for achieving both performance and energy efficiencies on heterogeneous systems. In: Field-Programmable Technology (FPT) (2014)
Giefers, H., Polig, R., Hagleitner, C.: Accelerating arithmetic kernels with coherent attached FPGA coprocessors. In: Design, Automation and Test in Europe (DATE), Germany (2015)
Liu, F., Solihin, Y.: Studying the impact of hardware prefetching and bandwidth partitioning in chip-multiprocessors. In: Proceedings of the ACM SIGMETRICS (2011)
Lee, C., Mutlu, O., Narasiman, V., Patt, Y.: Prefetch-aware DRAM controller. In: Proceedings of the 41th IEEE/ACM International Symposium on Microarchitecture (MICRO) (2008)
Rafique, N., Lim, W., Thottethodi, M.: Effective management of DRAM bandwidth in multicore processors. In: Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT) (2007)
Sklyarov, V., Skliarova, I.: High-performance implementation of regular and easily scalable sorting networks on an FPGA. Microprocess. Microsyst. 38(5), 470–484 (2014)
Lafond, S., Lilius, J.: Interrupt costs in embedded system with short latency hardware accelerators. In: Engineering of Computer Based Systems, pp. 317–325 (2008)
Xilinx Co.: Zynq-7000 All Programmable SoC Technical Reference Manual (2014)
Avnet Co.: ZedBoard Hardware Users Guide (2014)
Arm Co.: Cortex-A9 MPCore Technical Reference Manual (2012)
Arm Co.: AMBA AXI and ACE Protocol Specification (2013)
Xilinx Co.: LogiCORE IP AXI Interconnect v2 (2013)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer International Publishing Switzerland
About this paper
Cite this paper
Tahghighi, M., Sinha, S., Zhang, W. (2016). Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA. In: Bonato, V., Bouganis, C., Gorgon, M. (eds) Applied Reconfigurable Computing. ARC 2016. Lecture Notes in Computer Science(), vol 9625. Springer, Cham. https://doi.org/10.1007/978-3-319-30481-6_13
Download citation
DOI: https://doi.org/10.1007/978-3-319-30481-6_13
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-30480-9
Online ISBN: 978-3-319-30481-6
eBook Packages: Computer ScienceComputer Science (R0)