Programmable Logic as Device Virtualization Layer in Heterogeneous Multicore Architectures

Abstract

In latest heterogeneous multicore architectures, the number of cores competing for a shared resource is further increasing. Such shared resources range from simple I/O interfaces to memory controllers. The performance of the complete System-On-Chip (SoC) is directly correlated to the sharing of resources. Especially the hardly predictable blocking of resources for a certain time, forces the system to slow down in a way that is not intended. Hence new concepts for the sharing of resources need to be developed. The use of virtualization provides possibilities to handle the sharing of resources but always introduces an overhead in software in form of a hypervisor and also needs support on hardware level. In this contribution we explore the idea of using the FPGA fabric as intermediate hardware virtualization layer between the cores and existing peripherals in a heterogeneous multicore SoC. This paper applies the idea exemplarily to Controller Area Network (CAN) virtualization, including concept and evaluation. We show the transparency of a virtualization layer and its introduction with low overhead of area and latency, which might serve as efficient add-on in a virtualized environment.