Abstract
The main contribution of this paper is to present an FPGA-targeted architecture called the hierarchical GCD cluster, that computes the GCDs of all pairs in a set of numbers. It is designed based on the FDFM (Few DSP slices and Few Memory blocks) approach and consists of 1408 processors equipped with one block RAM and one DSP slice each. Every processor works in parallel and computes the GCDs independently. We have measured the performance of our architecture to compute all pairs of two numbers in RSA moduli. Implementation results show that it runs 0.057\(\mu \)s per one GCD computation of two 1024-bit RSA moduli in a Xilinx Virtex-7 family FPGA XC7VX485T-2. It is 6.0 times faster than the best GPU implementation and 500 times faster than a sequential implementation on the Intel Xeon CPU.
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Zhou, X., Nakano, K., Ito, Y. (2016). Parallel FDFM Approach for Computing GCDs Using the FPGA. In: Wyrzykowski, R., Deelman, E., Dongarra, J., Karczewski, K., Kitowski, J., Wiatr, K. (eds) Parallel Processing and Applied Mathematics. PPAM 2015. Lecture Notes in Computer Science(), vol 9573. Springer, Cham. https://doi.org/10.1007/978-3-319-32149-3_23
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DOI: https://doi.org/10.1007/978-3-319-32149-3_23
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