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USB 3.1 Gen 1 Hub Time Delay Influence on System Timeout and Bus Clock Synchronization

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Computer Networks (CN 2016)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 608))

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Abstract

The USB device designer must be aware of the worst case total delay between the host and a peripheral, because this value is necessary for setting the transaction timeout (allowable response packet delay).

In the paper the problem of USB bus timeout is covered for different USB buses: Low/FullSpeed USB 1.x, HighSpeed USB 2.0 and SuperSpeed USB 3.1 Gen 1. The USB 3.1 bus time delay measurement results are presented and supremum of response time is estimated. Additionaly, time delay of isochronous timestamps broadcasting is considered. At last, the demand for adaptive setting of the USB 3.1 bus timeout is expressed.

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Notes

  1. 1.

    This 7.5 bit times delay is defined as the time from the EOP (End of Packet) to idle transition observed on the upstream end of the function cable until the SOP (Start of Packet) transition from the device is returned to upstream end of the target cable [1].

References

  1. Anderson, D.: Universal Serial Bus System Architecture. MindShare (1997)

    Google Scholar 

  2. Universal Serial Bus 2.0 Specification, Rev. 2.0-2000. www.usb.org

  3. Universal Serial Bus 3.0 Specification, Rev. 1.0-2011. www.usb.org

  4. Universal Serial Bus 3.1 Specification, Rev. 1.0-2013. www.usb.org

  5. Hyde, J.: SuperSpeed Device Design By Example (2015)

    Google Scholar 

  6. Ramadoss, L., Hung, J.Y.: A study on universal serial bus latency in a real-time control system. In: IEEE Industrial Electronics (2008)

    Google Scholar 

  7. Xylomenos, G., Tsilopoulos, C.: Adaptive timeout policies for wireless links. In: 20th International Conference on Advanced Information Networking and Applications (2006)

    Google Scholar 

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Author information

Authors and Affiliations

  1. Institute of Informatics, Silesian University of Technology, Akademicka 16, 44-100, Gliwice, Poland

    Wojciech Mielczarek & Michał Sawicki

Authors
  1. Wojciech Mielczarek
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  2. Michał Sawicki
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Corresponding author

Correspondence to Michał Sawicki .

Editor information

Editors and Affiliations

  1. Silesian University of Technology, Gliwice, Poland

    Piotr Gaj

  2. Silesian University of Technology, Gliwice, Poland

    Andrzej Kwiecień

  3. Silesian University of Technology, Gliwice, Poland

    Piotr Stera

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© 2016 Springer International Publishing Switzerland

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Mielczarek, W., Sawicki, M. (2016). USB 3.1 Gen 1 Hub Time Delay Influence on System Timeout and Bus Clock Synchronization. In: Gaj, P., Kwiecień, A., Stera, P. (eds) Computer Networks. CN 2016. Communications in Computer and Information Science, vol 608. Springer, Cham. https://doi.org/10.1007/978-3-319-39207-3_20

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  • DOI: https://doi.org/10.1007/978-3-319-39207-3_20

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-39206-6

  • Online ISBN: 978-3-319-39207-3

  • eBook Packages: Computer ScienceComputer Science (R0)

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