Abstract
A flexible data frame structure adapted to 5G operations and designed to support high bandwidth pipes or sporadic traffic is described. The frame structure imposes to consider receiver architectures that are adapted to orthogonal frequency division mutliplexing (OFDM) for structured synchronous traffic and alternative flexible asynchronous waveforms such as filterbank multicarrier (FBMC) for sporadic traffic. OFDM and FBMC receivers are reviewed and a new flexible receiver architecture is then proposed and described. The design of the new architecture is centered on a memory unit complemented with co-processor units improving the flexibility of the digital signal processing operations of the receiver. The architecture is particularly adapted to application specific integrated circuit. The throughput imposed on the memory and the associated data receiver bus has been evaluated. The evaluation concluded that the throughput is suitable for very large scale integration implementations.
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Acknowledgments
The research leading to these results was supported by the European Commission under grant agreement 671563 (H2020-ICT-2014-2 / ICT-14-2014), Flexible and efficient hardware/software platforms for 5G network elements and devices (Flex5GWare).
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© 2016 ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering
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Berg, V., Doré, JB. (2016). A Flexible 5G Receiver Architecture Adapted to VLSI Implementation. In: Noguet, D., Moessner, K., Palicot, J. (eds) Cognitive Radio Oriented Wireless Networks. CrownCom 2016. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 172. Springer, Cham. https://doi.org/10.1007/978-3-319-40352-6_40
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DOI: https://doi.org/10.1007/978-3-319-40352-6_40
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