Abstract
Scalable hardware interconnect is a significant research challenge for neuromorphic systems in particular, this becomes more pronounced when we seek to realise the integration of neurons with astrocytes cells. This paper presents a novel interactive architecture for the astrocyte-neuron network (ANN) hardware systems, and the novel Hierarchical Astrocyte Network Architecture (HANA) using networks-on-chip (NoC) for the efficient information exchange between astrocyte cells. The proposed HANA incorporates a two-level NoC packet transmission mechanism to increase the information exchange rate between astrocyte cells and to provide a NoC traffic balance for local and global astrocyte networks. Experimental results demonstrate that the proposed HANA approach can provide efficient information exchange rates for the ANN, while the hardware synthesis results using 90 nm CMOS technology show that it has a low area overhead which maintains scalability.
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Liu, J., Harkin, J., McDaid, L., Martin, G. (2016). Hierarchical Networks-on-Chip Interconnect for Astrocyte-Neuron Network Hardware. In: Villa, A., Masulli, P., Pons Rivero, A. (eds) Artificial Neural Networks and Machine Learning – ICANN 2016. ICANN 2016. Lecture Notes in Computer Science(), vol 9886. Springer, Cham. https://doi.org/10.1007/978-3-319-44778-0_45
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DOI: https://doi.org/10.1007/978-3-319-44778-0_45
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