Abstract
A spike decoding scheme for Address Event Representation (AER)-based transmission in Spiking Neural Network (SNN) emulators is introduced. The proposed scheme is a modified associative memory based on an efficient use of BRAM, supporting connectivity upgrade in real-time for hardware implementations of evolutionary networks. After analysing the different options and selecting the most efficient one, a prototype example based on FPGA is provided together with a novel hashing technique to demonstrate a compact on-chip solution for implementing inter-chip connectivity in SNN.
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Acknowledgments
Work supported in part by the Spanish Ministry of Science and Innovation under Project TEC2015-67278-R, and European Social Fund (ESF). Mireya Zapata holds a scholarship from National Secretary of High Education Science Technology and Innovation (SENACYT) of the Ecuadorian government.
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Zapata, M., Madrenas, J. (2016). Compact Associative Memory for AER Spike Decoding in FPGA-Based Evolvable SNN Emulation. In: Villa, A., Masulli, P., Pons Rivero, A. (eds) Artificial Neural Networks and Machine Learning – ICANN 2016. ICANN 2016. Lecture Notes in Computer Science(), vol 9886. Springer, Cham. https://doi.org/10.1007/978-3-319-44778-0_47
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DOI: https://doi.org/10.1007/978-3-319-44778-0_47
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