Abstract
The optimal deployment of data streaming applications onto multi-/many-core platforms providing real-time guarantees requires to solve the application partitioning/placement, buffer allocation, task mapping and scheduling optimisation problem using the tasks Worst-Case Execution Time (WCET). In turn, task WCET varies due to interferences that tasks experience when accessing shared resources, which vary depending on the solutions of the optimisation problem. To break this cyclic dependency we propose a detailed interference-based method that first over-approximates WCET based on the solution for application partitioning/placement and then tightens it by pruning out the interferences from tasks not overlapping in memory access and time. We prove that the derived bounds are safe. We have found that interferences on average amount to 10 % of WCET, and were able to improve the latency-guarantee up to 34 %.
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References
aiT: the industry standard for static timing analysis. http://www.absint.com/ait/
Bilsen, G., Engels, M., Lauwereins, R., Peperstraete, J.: Cycle-static dataflow. IEEE Trans. Sig. Process. 44(2), 397–408 (1996)
Burgio, P., Marongiu, A., Valente, P., Bertogna, M.: A memory-centric approach to enable timing-predictability within embedded many-core accelerators. In: 2015 CSI Symposium on Real-Time and Embedded Systems and Technologies (RTEST), pp. 1–8, October 2015
Cota, É., de Amory, A.M., Lubaszewski, M.S.: Reliability, Availability and Serviceability of Networks-on-chip. Springer Science & Business Media, New York (2011)
Cotton, S., Maler, O., Legriel, J., Saidi, S.: Multi-criteria optimization for mapping programs to multi-processors. In: 2011 6th IEEE International Symposium on Industrial Embedded Systems (SIES), pp. 9–17. IEEE (2011)
de Dinechin, B.D., van Amstel, D., Poulhiès, M., Lager, G.: Time-critical computing on a single-chip massively parallel processor. In: Proceedings of the Conference on Design, Automation & Test in Europe, DATE 2014, pp. 97:1–97:6. European Design and Automation Association, 3001 Leuven, Belgium (2014)
Dkhil, A., Louise, S., Rochange, C.: Worst-case communication overhead in a many-core based shared-memory model (regular paper). In: Junior Researcher Workshop on Real-Time Computing, Nice, pp. 53–56. University of Amsterdam, 16/10/2013-18/10/2013, Octobre 2013. http://www.uva.nl
Giannopoulou, G., Stoimenov, N., Huang, P., Thiele, L., de Dinechin, B.: Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources. Real-Time Syst. 51, 1–51 (2015)
Kadayif, I., Kandemir, M., Sezer, U.: An integer linear programming based approach for parallelizing applications in on-chip multiprocessors. In: DAC 2002, pp. 703–706. ACM, New York (2002)
Kalray. Kalray MPPA-256 (2015)
Legriel, J., Le Guernic, C., Cotton, S., Maler, O.: Approximating the pareto front of multi-criteria optimization problems. In: Esparza, J., Majumdar, R. (eds.) TACAS 2010. LNCS, vol. 6015, pp. 69–83. Springer, Heidelberg (2010)
Nelson, A., Goossens, K., Akesson, B.: Dataflow formalisation of real-time streaming applications on a composable and predictable multi-processor soc. J. Syst. Archit. 61(9), 435–448 (2015)
Nguyen, V.A., Hardy, D., Puaut, I.: Scheduling of parallel applications on many-core architectures with caches: bridging the gap between WCET analysis and schedulability analysis. In: 9th Junior Researcher Workshop on Real-Time Computing (JRWRTC 2015), Lille, France, November 2015
Srinivasan, A., Baruah, S.: Deadline-based scheduling of periodic task systems on multiprocessors. Inf. Process. Lett. 84(2), 93–98 (2002)
Tendulkar, P., Poplavko, P., Galanommatis, I., Maler, O.: Many-core scheduling of data parallel applications using smt solvers. In: 2014 17th Euromicro Conference on Digital System Design (DSD), pp. 615–622. IEEE (2014)
Tendulkar, P., Poplavko, P., Maler, O.: Symmetry breaking for multi-criteria mapping and scheduling on multicores. In: Braberman, V., Fribourg, L. (eds.) FORMATS 2013. LNCS, vol. 8053, pp. 228–242. Springer, Heidelberg (2013)
Texas Instruments Inc. The 66AK2H12 keystone II Processor
Thies, W., Amarasinghe, S.: An empirical characterization of stream programs and its implications for language and compiler design. In: Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, PACT 2010, pp. 365–376. ACM, New York (2010)
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The research work of this paper was funded by the Swiss Confederation through the UltrasoundToGo project of the Nano-Tera.ch initiative.
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Skalistis, S., Simalatsar, A. (2016). Worst-Case Execution Time Analysis for Many-Core Architectures with NoC. In: Fränzle, M., Markey, N. (eds) Formal Modeling and Analysis of Timed Systems. FORMATS 2016. Lecture Notes in Computer Science(), vol 9884. Springer, Cham. https://doi.org/10.1007/978-3-319-44878-7_13
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DOI: https://doi.org/10.1007/978-3-319-44878-7_13
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