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Loop Nest Tiling for Image Processing and Communication Applications

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Hard and Soft Computing for Artificial Intelligence, Multimedia and Security (ACS 2016)

Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 534))

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Abstract

Loop nest tiling is one of the most important loop nest optimizations. This paper presents a practical framework for automatic tiling of affine loop nests to reduce time of application execution which is crucial for the quality of image processing and communication systems. Our framework is derived via a combination of the Polyhedral and Iteration Space Slicing models and uses the transitive closure of loop nest dependence graphs. To describe and implement the approach in the source-to-source TRACO compiler, loop dependences are presented in the form of tuple relations. We expose the applicability of the framework to generate tiled code for image analysis, encoding and communication program loop nests from the UTDSP Benchmark Suite. Experimental results demonstrate the speed-up of optimized tiled programs generated by means of the approach implemented in TRACO.

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Notes

  1. 1.

    The notation x \(\ge \) (\(\le \)) y where x, y are two vectors in \(\mathbb {Z}^n\) corresponds to the component-wise inequality, that is, x \(\ge \) (\(\le \)) \(y\Longleftrightarrow x_i\) \(\ge \) (\(\le \)) \(y_{i}\), i=1,2,...,n.

  2. 2.

    “\(\prec \)” and “\(\succ \)” denote the lexicographical relation operators for two vectors.

  3. 3.

    Source codes with tiled version are available at the TRACO repository http://sourceforge.net/p/traco/code/HEAD/tree/trunk/examples/utdsp/.

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Authors and Affiliations

  1. Faculty of Computer Science and Information Systems, West Pomeranian University of Technology in Szczecin, Zolnierska 49, 71210, Szczecin, Poland

    Wlodzimierz Bielecki & Marek Palkowski

Authors
  1. Wlodzimierz Bielecki
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  2. Marek Palkowski
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Correspondence to Wlodzimierz Bielecki .

Editor information

Editors and Affiliations

  1. Graduate School of Science and Engineeri, Ehime University Graduate School of Science and Engineeri, Ehime, Japan

    Shin-ya Kobayashi

  2. West Pomeranian University of Technology in Szczecin , Szczecin, Poland

    Andrzej Piegat

  3. West Pomeranian University of Technology in Szczecin , Szczecin, Poland

    Jerzy Pejaś

  4. West Pomeranian University of Technology in Szczecin , Szczecin, Poland

    Imed El Fray

  5. Polish Academy of Sciences, Systems Research Institute Polish Academy of Sciences, Warsaw, Poland

    Janusz Kacprzyk

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Bielecki, W., Palkowski, M. (2017). Loop Nest Tiling for Image Processing and Communication Applications. In: Kobayashi, Sy., Piegat, A., Pejaś, J., El Fray, I., Kacprzyk, J. (eds) Hard and Soft Computing for Artificial Intelligence, Multimedia and Security. ACS 2016. Advances in Intelligent Systems and Computing, vol 534. Springer, Cham. https://doi.org/10.1007/978-3-319-48429-7_28

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  • DOI: https://doi.org/10.1007/978-3-319-48429-7_28

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