Abstract
In this paper, a new hierarchical view of the workload phase classification problem is introduced. Execution phases are the continuous pieces of execution that show consistent behaviour in terms of performance and power. To the best of our knowledge, this is the first work which uses a hierarchical approach to collect and cluster the performance monitoring counters in order to detect macroscopic phases in an application. Our results show the ability of our model to differentiate between execution phases according to the processor power behaviour. Furthermore, we investigate the power consistency inside each phase. The results show the effectiveness of our proposed methodology in classifying phases with similar power behaviour. This information can be used by the system to control and maintain power bursts, increasing the data centre’s power efficiency by reducing the maximum-to-average power ratio.
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References
Srinivasan, S., Kumar, R., Kundu, S.: Program phase duration prediction and its application to fine-grain power management. In: 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 127–132, August 2013
Benomar, O., Sahraoui, H., Poulin, P.: Detecting program execution phases using heuristic search. In: Goues, C., Yoo, S. (eds.) SSBSE 2014. LNCS, vol. 8636, pp. 16–30. Springer, Cham (2014). doi:10.1007/978-3-319-09940-8_2
Fan, X., Weber, W.-D., Barroso, L.A.: Power provisioning for a warehouse-sized computer. In: Proceedings of the 34th Annual International Symposium on Computer Architecture. ISCA 2007, pp. 13–23. ACM (2007)
Henning, J.L.: SPEC CPU2006 benchmark descriptions. ACM SIGARCH Comput. Archit. News 34(4), 1–17 (2006)
Reiss, S.P.: Dynamic detection and visualization of software phases. ACM SIGSOFT Softw. Eng. Notes 30(4), 1–6 (2005)
Ishio, T., Watanabe, Y., Inoue, K.: AMIDA: A sequence diagram extraction toolkit supporting automatic phase detection. In: Companion of the 30th International Conference on Software Engineering, pp. 969–970. ACM (2008)
Isci, C., Martonosi, M.: Phase characterization for power: evaluating control-flow-based and event-counter-based techniques. In: HPCA 2006, pp. 121–132 (2006)
Zhang, Z., Chang, J.M.: A cool scheduler for multi-core systems exploiting program phases. IEEE Trans. Comput. 63(5), 1061–1073 (2014)
Cochran, R., Reda, S.: Thermal prediction and adaptive control through workload phase detection. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 18(1), 7 (2013)
Mucci, P.J., Browne, S., Deane, C., Ho, G.: PAPI: A portable interface to hardware performance counters. In: Proceedings of the Department of Defense HPCMP Users Group Conference, pp. 7–10 (1999)
Sun, Y., Wanner, L., Srivastava, M.: Low-cost estimation of sub-system power. In: International Green Computing Conference (IGCC), pp. 1–10. IEEE (2012)
Kim, Y., Park, S., Cho, Y., Chang, N.: System-level online power estimation using an on-chip bus performance monitoring unit. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11), 1585–1598 (2011)
Bartalos, P., Blake, M.B.: Green web services: modeling and estimating power consumption of web services. In: 2012 IEEE 19th International Conference on Web Services (ICWS), pp. 178–185. IEEE (2012)
Khoshbakht, S., Dimopoulos, N.: SAPPP: the software-aware power and performance profiler (under Review)
Hardy, A.: An examination of procedures for determining the number of clusters in a data set. In: Diday, E., Lechevallier, Y., Schader, M., Bertrand, P., Burtschy, B. (eds.) New Approaches in Classification and Data Analysis. Studies in Classification, Data Analysis, and Knowledge Organization, pp. 178–185. Springer, Heidelberg (1994). doi:10.1007/978-3-642-51175-2_20
Bircher, W.L., John, L.K.: Complete system power estimation using processor performance events. IEEE Trans. Comput. 61(4), 563–577 (2012)
Rodrigues, R., Annamalai, A., Koren, I., Kundu, S.: Scalable thread scheduling in asymmetric multicores for power efficiency. In: 2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), pp. 59–66. IEEE (2012)
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Khoshbakht, S., Dimopoulos, N. (2017). A New Approach to Detecting Execution Phases Using Performance Monitoring Counters. In: Knoop, J., Karl, W., Schulz, M., Inoue, K., Pionteck, T. (eds) Architecture of Computing Systems - ARCS 2017. ARCS 2017. Lecture Notes in Computer Science(), vol 10172. Springer, Cham. https://doi.org/10.1007/978-3-319-54999-6_7
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DOI: https://doi.org/10.1007/978-3-319-54999-6_7
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