Abstract
A trading strategy is generally optimised for a given market regime. If it takes too long to switch from one trading strategy to another, then a sub-optimal trading strategy may be adopted. This paper proposes the first FPGA-based framework which supports multiple trend-following trading strategies to obtain accurate market characterisation for various financial market regimes. The framework contains a trading strategy kernel library covering a number of well-known trend-following strategies, such as “triple moving average”. Three types of design are targeted: a static reconfiguration trading strategy (SRTS), a full reconfiguration trading strategy (FRTS), and a partial reconfiguration trading strategy (PRTS). Our approach is evaluated using both synthetic and historical market data. Compared to a fully optimised CPU implementation, the SRTS design achieves 11 times speedup, the FRTS design achieves 2 times speedup, while the PRTS design achieves 7 times speedup. The FRTS and PRTS designs also reduce the amount of resources used on chip by 29% and 15% respectively, when compared to the SRTS design.
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References
Wray, S., et al.: Exploring algorithmic trading in reconfigurable hardware. In: ASAP (2010)
Altera. FPGA Run-Time Reconfiguration: Two Approaches - White Paper. ftp://ftp.bittware.com/documents/fpga-run-time-reconfiguration.pdf
Driver, M.: Foreign Exchange: A Practical Guide to the FX Markets. CreateSpace, North Charleston (2012)
Aldridge, I.: High-Frequency Trading: A Practical Guide to Algorithmic Strategies and Trading Systems (Wiley Trading), 2nd edn. Wiley, Hoboken (2013)
Maxeler Technologies, MaxCompiler-WhitePaper (2001). https://www.maxeler.com/media/documents/MaxelerWhitePaperMaxCompiler.pdf
Leber, C., et al.: High frequency trading acceleration using FPGAs. In: FPL (2011)
Mastinu, M.: Design flow to support dynamic partial reconfiguration on Maxeler architectures. Politecnico di Milano (2012)
Funie, A.I., et al.: Reconfigurable acceleration of fitness evaluation in trading strategies. In: ASAP (2015)
Guo, C., et al.: Pipelined reconfigurable accelerator for ordinal pattern encoding. In: ASAP (2014)
Acknowledgments
The support of UK EPSRC (EP/I012036/1, EP/L00058X/1, EP/L016796/1 and EP/N031768/1), the European Union Horizon 2020 Research and Innovation Programme under grant agreement number 671653, the China Scholarship Council, the Maxeler University Programme, Altera, Intel and Xilinx is gratefully acknowledged.
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Funie, AI., Guo, L., Niu, X., Luk, W., Salmon, M. (2017). Custom Framework for Run-Time Trading Strategies. In: Wong, S., Beck, A., Bertels, K., Carro, L. (eds) Applied Reconfigurable Computing. ARC 2017. Lecture Notes in Computer Science(), vol 10216. Springer, Cham. https://doi.org/10.1007/978-3-319-56258-2_14
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DOI: https://doi.org/10.1007/978-3-319-56258-2_14
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