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An FPGA-Based Implementation of a Pipelined FFT Processor for High-Speed Signal Processing Applications

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Applied Reconfigurable Computing (ARC 2017)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 10216))

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Abstract

In this study, we propose an efficient, 1024 point, pipelined FFT processor based on the radix-2 decimation-in-frequency (R2DIF) algorithm using the single-path delay feedback (SDF) pipelined architecture. The proposed FFT processor is designed as an intellectual property (IP) logic core for easy integration into digital signal processing (DSP) systems. It employs the shift-add method to optimize the multiplication of twiddle factors instead of the dedicated, embedded functional blocks. The proposed design is implemented on a Xilinx Virtex-7 field programmable gate array (FPGA). The experimental results show that the proposed FFT design is more efficient in terms of speed, accuracy and resource utilization as compared to existing designs and hence more suitable for high-speed DSP applications.

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Acknowledgments

This work was supported by the Korea Institute of Energy Technology Evaluation and Planning(KETEP) and the Ministry of Trade, Industry & Energy (MOTIE) of the Republic of Korea (No. 20161120100350, No. 20162220100050), in part by The Leading Human Resource Training Program of Regional Neo industry through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT and future Planning (NRF-2016H1D5A1910564), in part by Business for Cooperative R&D between Industry, Academy, and Research Institute funded Korea Small and Medium Business Administration in 2016 (Grants No. C0395147, Grants S2381631), and in part by the development of a basic fusion technology in electric power industry (Ministry of Trade, Industry & Energy, 201301010170D).

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Authors and Affiliations

  1. School of Electrical Engineering, University of Ulsan, Ulsan, South Korea

    Ngoc-Hung Nguyen, Sheraz Ali Khan & Jong-Myon Kim

  2. School of Electronics and Computer Engineering, Chonnam National University, Gwangju, 61186, South Korea

    Cheol-Hong Kim

Authors
  1. Ngoc-Hung Nguyen
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  2. Sheraz Ali Khan
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  3. Cheol-Hong Kim
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  4. Jong-Myon Kim
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Corresponding author

Correspondence to Jong-Myon Kim .

Editor information

Editors and Affiliations

  1. Delft University of Technology, Delft, The Netherlands

    Stephan Wong

  2. Federal University of Rio Grande do Sul, Porto Alegre, Brazil

    Antonio Carlos Beck

  3. Delft University of Technology, Delft, The Netherlands

    Koen Bertels

  4. Federal University of Rio Grande do Sul, Porto Alegre, Brazil

    Luigi Carro

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Nguyen, NH., Khan, S.A., Kim, CH., Kim, JM. (2017). An FPGA-Based Implementation of a Pipelined FFT Processor for High-Speed Signal Processing Applications. In: Wong, S., Beck, A., Bertels, K., Carro, L. (eds) Applied Reconfigurable Computing. ARC 2017. Lecture Notes in Computer Science(), vol 10216. Springer, Cham. https://doi.org/10.1007/978-3-319-56258-2_8

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  • DOI: https://doi.org/10.1007/978-3-319-56258-2_8

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-56257-5

  • Online ISBN: 978-3-319-56258-2

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