Design of Processor in Memory with RISC-modified Memory-Centric Architecture

Abstract

The technological developments in the areas of computer hardware and software resulted in a wide range of fast and cheap single- or multi-core processors, compilers, operating systems and programming languages, each with its own benefits and drawbacks, but with the ultimate goal to increase overall computer system performances. Although the number of transistors on a chip continues to double roughly every two years, there is still difficult to improve the performance of sequential processors, and even of the parallel multi-core and multi-processor shared-memory systems. The main reason for this resides in the ever-increasing gap between processor and memory speeds in the classical Von Neumann’s computer model. Therefore in this paper we propose a novel memory-centric approach of computing in a RISC-modified processor core that includes on-chip memory, which can be directly accessed, without the use of general-purpose registers (GPRs) and cache memory. Considering that the proposed RISC-modified core allows for a high on-chip memory bandwidth and low latency, we examine its performances in applications with different arithmetical intensity (dense matrix multiplication, Fast Fourier Transform - FFT, Partial Differential Equations - PDEs), according to the Roofline model. The results show that the proposed memory-centric RISC-modified core outperforms the initial RISC-based MIPS processor core for problems with medium or large arithmetical intensity.