Abstract
This paper describes the method for hardware implementation of the emulator of nonlinear dynamic objects in FPGA technology. In order to ensure high-fidelity of emulation it has been proposed a new architecture of the arithmetic unit used to operations on real numbers in digital systems. The method allows us to obtain high processing performance similar to that obtained in fixed-point systems, while offering a wide range of numbers as in a floating-point notation. Based on this idea it has been proposed a super-scalar architecture of the digital processing unit. The described approach provides powerful processing of a matrix state equation with variable coefficients, which are calculated in real-time by fuzzy systems. Obtained and presented results confirm the high performance of the developed solution.
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The project was financed by the National Science Centre (Poland) on the basis of the decision number DEC-2012/05/B/ST7/02138.
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Przybył, A., Er, M.J. (2017). A Method for Design of Hardware Emulators for a Distributed Network Environment. In: Rutkowski, L., Korytkowski, M., Scherer, R., Tadeusiewicz, R., Zadeh, L., Zurada, J. (eds) Artificial Intelligence and Soft Computing. ICAISC 2017. Lecture Notes in Computer Science(), vol 10246. Springer, Cham. https://doi.org/10.1007/978-3-319-59060-8_29
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