Abstract
In order to make full use of the memory resources of computers, especially embedded systems, the multiplexing of storage space in register spilling is investigated and the corresponding method is presented in this paper. This method is based on the graph coloring register allocation method and on the basic principle of greedy algorithm. In this method, the register allocation candidates to be spilled, which do not conflict with each other, will be spilled to the same memory unit. Thus, in register spilling, less memory is needed and more load/store instructions using immediate values can be used. The effectiveness of the method is verified. Besides, the method is suitable for architectures with both scalar and vector operands.
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References
Poletto, M.: Linear scan register allocation. ACM Trans. Program. Lang. Syst. 21, 895–913 (1999)
Briggs, P., Cooper, K., Kennedy, K., Torczon, L.: Coloring heuristics for register allocation. ACM SIGPLAN Not. 39, 275–284 (1989)
Colombet, Q., Brandner, F., Darte, A.: Studying optimal spilling in the light of SSA. In: 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, Taipei, pp. 25–34 (2011)
Tavares, A., Colombet, Q., Bigonha, M.: Decoupled graph-coloring register allocation with hierarchical aliasing. In: Proceedings of the 14th International Workshop on Software and Compilers for Embredded Systems, Goar, Germany, pp. 1–10 (2011)
Colombet, Q., Boissinot, B., Brisk, P.: Graph-coloring and tree scan register allocation using repairing. In: 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, Taipei, pp. 45–54 (2011)
Diouf, B., Cohen, A., Rastello, F.: A polynomial spilling heuristic: layered allocation. R. Research Report, Project-Teams Parkas and Compsys (2012)
Chaitin, G., Auslander, M., Chandra, A.: Register allocation via coloring. J. Comput. Lang. 6, 47–57 (1981)
Carole, D.-G., Hugues, F., Eli, G., Leslie, L.: Adaptive register allocation with a linear number of registers. In: 27th International Symposium, DISC 2013, Jerusalem, Israel, 14–18 October (2013)
Steven, S.: Advanced Compiler Design and Implementation. Elsevier Science, Amsterdam (1997). M. USA
Salgado, M., Ragel, R.G.: Register spilling for specific application domains in ASIPs. In: 7th International Conference on Information and Automation for Sustainability. IEEE (2014)
Wu, C., Lu, C., Lee, J.: Register spilling via transformed interference equations for PAC DSP architecture. Concurrency Comput. Pract. Experience 26, 779–799 (2014)
Pfenning, F., Simmons, R.: Lecture Notes on Register Allocation Optimizations (2015). http://www.cs.cmu.edu/~rjsimmon/15411-f15/lec/17-regopt.pdf
Yin, M., Steve, C., Rong, G.: Low-cost register-pressure prediction for scalar replacement using pseudo-schedules. In: 2004 International Conference on Parallel Processing, 0190–3918/04 (2004)
Shobaki, G., Shawabkeh, M., Rmaileh, N.: Preallocation instruction scheduling with register pressure minimization using a combinatorial optimization approach. ACM Trans. Archit. Code Optim. 10, 14 (2013)
Philipp. K., Frankfurt, M.: Bytewise register allocation. In: 18th International Workshop on Software and Compilers for Embedded Systems, New York (2015). 978-1-4503-3593-5
Gaow, Z., Han, L., Pang, J.: Research on SIMD auto-vectorization compiling optimization. J. Softw. 26, 1265–1284 (2015)
Acknowledgment
This work was supported by National Natural Science Foundation of China (Grant No. 61308001) and graduate student innovation fund project (Grant Nos.S140027 and CX2015B537).
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© 2017 ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering
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Li, G., Hu, Y., Qiu, Y., Huang, W. (2017). Investigation on the Optimization for Storage Space in Register-Spilling. In: Wang, S., Zhou, A. (eds) Collaborate Computing: Networking, Applications and Worksharing. CollaborateCom 2016. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 201. Springer, Cham. https://doi.org/10.1007/978-3-319-59288-6_63
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DOI: https://doi.org/10.1007/978-3-319-59288-6_63
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