Power Performance Analysis of FPGA-Based Particle Filtering for Realtime Object Tracking

Abstract

Real-time image processing with a compact FPGA-based architecture plays a key role in dynamic state-space models. This paper presents an energy efficient FPGA acceleration architecture of a particle filter, which is based on stream processing structure with a parallel resampling algorithm. Particle filters solve the state estimation problems with three steps: prediction, likelihood calculation and resampling. By accomplishing the resampling in a valid pixel area of an input image frame, while executing prediction in a synchronization region, our approach achieves real-time object tracking. This paper mainly highlights implementation alternatives using different clock frequencies and resource usages of FPGA. The result shows the comparisons of power consumption for the compact architecture with an accelerated clock frequency (135 MHz) compared to the larger circuit size with clock frequency (27 MHz). Interestingly, the larger architecture with a slower clock frequency shows lower power consumption.