Skip to main content

A Cross-Core Performance Model for Heterogeneous Many-Core Architectures

  • Conference paper
  • First Online:
High Performance Computing for Computational Science – VECPAR 2016 (VECPAR 2016)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 10150))

Included in the following conference series:

  • 415 Accesses

Abstract

An accurate performance predictor to identify the most suitable core-architecture to execute each thread/workload in a heterogeneous many-core structure is proposed. The devised predictor is based on a linear regression model that considers several different parameters of the many-core processor architectures, including the cache size, issue-width, re-order buffer size, load/store queues size, etc. The devised predictor is easily integrated in most system schedulers, providing the ability to periodically determine whether a certain thread is running in the most efficient core-architecture. The obtained experimental results show that the devised model is able to identify the correct core-architecture in a large majority of the cases, leading to average performance differences as low as 7% when compared with an oracle scheduling solution.

This work was partially supported by national funds through Fundação para a Ciência e a Tecnologia (FCT), under project UID/CEC/50021/2013.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. big.LITTLE Technology: The Future of Mobile. Technical report, ARM (2011). https://www.arm.com/files/pdf/big_LITTLE_Technology_the_Futue_of_Mobile.pdf

  2. Bienia, C.: Benchmarking Modern Multiprocessors. Ph.D. thesis, Princeton University, Princeton, NJ, USA (2011)

    Google Scholar 

  3. Carlson, T.E., Heirman, W., Eyerman, S., Hur, I., Eeckhout, L.: An evaluation of high-level mechanistic core models. ACM Trans. Archit. Code Optim. (TACO) 11(3), 28:1–28:25 (2014)

    Google Scholar 

  4. Delimitrou, C., Kozyrakis, C.: Paragon: Qos-aware scheduling for heterogeneous datacenters. In: Proceedings of the Eighteenth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2013, pp. 77–88. ACM, New York (2013)

    Google Scholar 

  5. Gaspar, F., Taniça, L., Tomás, P., Ilic, A., Sousa, L.: A framework for application-guided task management on heterogeneous embedded systems. ACM Trans. Archit. Code Optim. 12(4), 42:1–42:25 (2015)

    Google Scholar 

  6. Imes, C., Kim, D.H., Maggio, M., Hoffmann, H.: POET: a portable approach to minimizing energy under soft real-time constraints. In: Proceedings of the Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 75–86. IEEE (2015)

    Google Scholar 

  7. Kumar, R., Farkas, K.I., et al.: Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction. In: 36th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 36, pp. 81–92. IEEE Computer Society (2003)

    Google Scholar 

  8. Kumar, R., Tullsen, D.M., et al.: Single-ISA heterogeneous multi-core architectures for multithreaded workload performance. SIGARCH Comput. Archit. News 32(2), 64–75 (2004)

    Article  Google Scholar 

  9. Patsilaras, G., Choudhary, N.K., Tuck, J.: Efficiently exploiting memory level parallelism on asymmetric coupled cores in the dark silicon era. ACM Trans. Architect. Code Optim. (TACO) 8(4), 28:1–28:21 (2012)

    Google Scholar 

  10. Pricopi, M., Muthukaruppan, T.S., et al.: Power-performance modeling on asymmetric multi-cores. In: 2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), pp. 1–10 (2013)

    Google Scholar 

  11. Saez, J.C., Prieto, M., et al.: A comprehensive scheduler for asymmetric multicore systems. In: 5th European Conference on Computer Systems, EuroSys 2010, pp. 139–152. ACM (2010)

    Google Scholar 

  12. Seber, G.A.F., Lee, A.J.: Linear Regression Analysis. Wiley, New York (2003)

    Google Scholar 

  13. Shelepov, D., Saez Alcaide, J.C., Jeffery, S., Fedorova, A., Perez, N., Huang, Z.F., Blagodurov, S., Kumar, V.: HASS: a scheduler for heterogeneous multicore systems. SIGOPS Oper. Syst. Rev. 43(2), 66–75 (2009)

    Google Scholar 

  14. Tibshirani, R.: Regression shrinkage and selection via the lasso. J. Roy. Stat. Soc. Ser. B (Methodological) 58, 267–288 (1996)

    Google Scholar 

  15. Van Craeynest, K., Jaleel, A., et al.: Scheduling heterogeneous multi-cores through performance impact estimation (PIE). In: 39th International Symposium on Computer Architecture, ISCA 2012, pp. 213–224. IEEE Computer Society (2012)

    Google Scholar 

  16. Zhu, Y., Halpern, M., Reddi, V.J.: Event-based scheduling for energy-efficient QoS (eQoS) in mobile web applications. In: Proceedings of the International Symposium on High Performance Computer Architecture (HPCA), pp. 137–149. IEEE (2015)

    Google Scholar 

  17. Zou, H., Hastie, T.: Regularization and variable selection via the elastic net. J. Roy. Stat. Soc. Ser. B (Statistical Methodology) 67(2), 301–320 (2005)

    Article  MathSciNet  MATH  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Pedro Tomás .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2017 Springer International Publishing AG

About this paper

Cite this paper

Pinheiro, R., Roma, N., Tomás, P. (2017). A Cross-Core Performance Model for Heterogeneous Many-Core Architectures. In: Dutra, I., Camacho, R., Barbosa, J., Marques, O. (eds) High Performance Computing for Computational Science – VECPAR 2016. VECPAR 2016. Lecture Notes in Computer Science(), vol 10150. Springer, Cham. https://doi.org/10.1007/978-3-319-61982-8_11

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-61982-8_11

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-61981-1

  • Online ISBN: 978-3-319-61982-8

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics