Skip to main content
SpringerLink
Log in
Book cover

International Conference on Vector and Parallel Processing

VECPAR 2016: High Performance Computing for Computational Science – VECPAR 2016 pp 174–187Cite as

Versat, a Minimal Coarse-Grain Reconfigurable Array

  • Conference paper
  • First Online:

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 10150))

Abstract

This paper introduces Versat, a minimal Coarse-Grain Reconfigurable Array (CGRA) used as a hardware accelerator to optimize performance and power in a heterogeneous system. Compared to other works, Versat features a smaller number of functional units and a simpler controller, mainly used for reconfiguration and data transfer control. This stems from the observation that competitive acceleration can be achieved with a smaller array and more flexible reconfigurations. Partial reconfiguration plays a central role in Versat’s runtime reconfiguration scheme. Results on core area, frequency, power and performance are presented and compared to other implementations.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

References

  1. De Sutter, B., Raghavan, P., Lambrechts, A.: Coarse-grained reconfigurable array architectures. In: Bhattacharyya, S.S., Deprettere, E.F., Leupers, R., Takala, J. (eds.) Handbook of Signal Processing Systems, pp. 449–484. Springer, Heidelberg (2010)

    Chapter  Google Scholar 

  2. Liu, L., Wang, D., Zhu, M., Wang, Y., Yin, S., Cao, P., Yang, J., Wei, S.: An energy-efficient coarse-grained reconfigurable processing unit for multiple-standard video decoding. IEEE Trans. Multimed. 17(10), 1706–1720 (2015)

    Article  Google Scholar 

  3. Lee, M.H., Singh, H., Lu, G., Bagherzadeh, N., Kurdahi, F.J.: Design and implementation of the MorphoSys reconfigurable computing processor. J. VLSI Signal Process. Syst. Signal Image Video Technol. 24, 147–164. Kluwer Academic Publishers (2000)

    Google Scholar 

  4. Mei, B., Lambrechts, A., Mignolet, J.-Y., Verkest, D., Lauwereins, R.: Architecture exploration for a reconfigurable architecture template. Des. Test Comput. 22(2), 90–101 (2005)

    Article  Google Scholar 

  5. de Sousa, J.T., Martins, V.M.G., Lourenco, N.C.C., Santos, A.M.D., do Rosario Ribeiro, N.G.: Reconfigurable coprocessor architecture template for nested loops and programming tool. US Patent 8,276,120 (2012)

    Google Scholar 

  6. Hartenstein, R., Herz, M., Hoffmann, T., Nageldinger, U.: Mapping applications onto reconfigurable KressArrays. In: Lysaght, P., Irvine, J., Hartenstein, R. (eds.) FPL 1999. LNCS, vol. 1673, pp. 385–390. Springer, Heidelberg (1999). doi:10.1007/978-3-540-48302-1_42

    Chapter  Google Scholar 

  7. Ebeling, C., Cronquist, D.C., Franklin, P.: RaPiD — reconfigurable pipelined datapath. In: Hartenstein, R.W., Glesner, M. (eds.) FPL 1996. LNCS, vol. 1142, pp. 126–135. Springer, Heidelberg (1996). doi:10.1007/3-540-61730-2_13

    Chapter  Google Scholar 

  8. Baumgarte, V., Ehlers, G., May, F., Nückel, A., Vorbach, M., Weinhardt, M.: PACT XPP - a self-reconfigurable data processing architecture. J. Supercomput. 26(2), 167–184 (2003)

    Article  MATH  Google Scholar 

  9. Farahini, N., Hemani, A., Sohofi, H., Jafri, S.M.A.H., Tajammul, M.A., Paul, K.: Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric. Microprocess. Microsyst. 38(8), 788–802 (2014)

    Article  Google Scholar 

  10. Liu, D., Yin, S., Liu, L., Wei, S.: Polyhedral model based mapping optimization of loop nests for CGRAs. In: 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1–8 (2013)

    Google Scholar 

  11. Wang, W., Dey, T.: A survey on ARM Cortex A processors. http://www.cs.virginia.edu/skadron/cs8535s11/armcortex.pdf. Accessed 6 Apr 2016

  12. Huang, W., Rajamani, K., Stan, M.R., Skadron, K.: Scaling with design constraints: predicting the future of big chips. IEEE Micro 31(4), 16–29 (2011)

    Article  Google Scholar 

  13. Kamalizad, A.H., Pan, C., Bagherzadeh, N.: Fast parallel FFT on a reconfigurable computation platform. In: 15th Symposium on Computer Architecture and High Performance Computing, Proceedings, pp. 254–259 (2003)

    Google Scholar 

Download references

Acknowledgment

This work was supported by national funds through Fundação para a Ciência e a Tecnologia (FCT) with reference UID/CEC/50021/2013.

Author information

Authors and Affiliations

  1. INESC-ID/IST, University of Lisbon, Lisbon, Portugal

    João D. Lopes & José T. de Sousa

Authors
  1. João D. Lopes
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. José T. de Sousa
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to José T. de Sousa .

Editor information

Editors and Affiliations

  1. University of Porto, Porto, Portugal

    Inês Dutra

  2. University of Porto, Porto, Portugal

    Rui Camacho

  3. University of Porto, Porto, Portugal

    Jorge Barbosa

  4. Lawrence Berkeley National Laboratory, Berkeley, California, USA

    Osni Marques

Rights and permissions

Reprints and permissions

Copyright information

© 2017 Springer International Publishing AG

About this paper

Cite this paper

Lopes, J.D., de Sousa, J.T. (2017). Versat, a Minimal Coarse-Grain Reconfigurable Array. In: Dutra, I., Camacho, R., Barbosa, J., Marques, O. (eds) High Performance Computing for Computational Science – VECPAR 2016. VECPAR 2016. Lecture Notes in Computer Science(), vol 10150. Springer, Cham. https://doi.org/10.1007/978-3-319-61982-8_17

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-61982-8_17

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-61981-1

  • Online ISBN: 978-3-319-61982-8

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation